Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Hisakazu Sato

Shinji Komori

Hidehiro Takata

Toshiyuki Tamura

Akira Yamada

Toyohiko Yoshida

Isao Minematsu

Hironobu Ito

Masaki Fujita

Shunichi Iwata

Takeshi Kataoka

Kesami Hagiwara

Yoshikazu Kiyoshige

Yoshihiro Seguchi

Akihiko Tomita

When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

Data processing apparatus of high speed process using memory of low speed and low power consumption

In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

Data processing system

An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.

Semiconductor memory device storing part of program designated by programmer, and software development apparatus for system using the same

A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.

Data processing device capable of reading and writing of double precision data in one cycle

A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and a program counter control unit controlling a value of a program counter for providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during a consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced. This renders it possible to branch to an operation instruction executed during a consecutive execution and thus provide an enhanced efficiency of instruction-code compression.

VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively

A data processor configured to repeatedly perform sequential execution of a plurality of instructions in a program in response to a repeat instruction in the program. The data processor includes a counting circuit configured to count every time one instruction of the plurality of instructions is executed; a judgment circuit configured to judge whether the counting circuit counts a predetermined number of times; and an instruction execution control portion configured to control an execution sequence to return to a head instruction of said plurality of instructions following a last instruction in the plurality of instructions in response to a first result output from the judgment circuit indicating that the counting circuit does not count the predetermined number of times.

Data processor having repeat instruction processing using executed instruction number counter

A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address in data memory is provided between the data memory and a data path unit. The alignment buffer outputs misaligned data by selecting misaligned data from data held in the register and data read from the data memory. The data held in the register is updated as word-aligned data is read out.

Data processor changing an alignment of loaded data

A tag array retains a plurality of tag data, and performs matching of the tag data with a retrieval keyword. The tag array includes matching circuits provided corresponding to the tag data. Each of the matching circuits has CM and CC cells provided corresponding to a plurality of bits of the corresponding tag data. Each CM cell retains a corresponding bit of the tag data, and performs matching of the retaining bit with a corresponding bit of the retrieval keyword. Each CC cell, not only functions as the CM cell, but also retains a comparison condition signal input in advance, and invalidates, according to the comparison condition signal, the mismatch detected between corresponding bits of the tag data and the retrieval keyword. As a result, it becomes possible to variably set the number of bits, of an input retrieval keyword, being matched with the tag data.

Decoding device with associative memory permitting variable-length keyword comparisons

An execution control signal generation unit ( ) sequentially generates an execution control signal on the basis of an instruction code ( ) given through a group ( ) of data latches to execute an instruction designated by the instruction code ( ) when a repeat end flag ( ) is not asserted (instructions have not been yet executed an execution instruction number of times) and negates all the execution control signals, regardless of the indication of the instruction code ( ), when the repeat end flag ( ) is asserted (instructions have been executed the execution instruction number of times). All the instructions executed while the repeat end flag ( ) is asserted are negated. With this configuration, a data processor capable of executing instructions accurately a designated number of times while the instructions included in a predetermined instruction stream are repeatedly executed.

Versatile branch-less sequence control of instruction stream containing step repeat loop block using executed instructions number counter

A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence control section (5) has two control registers (VL.sub.-- MODE and VL.sub.-- CNT). A CPU (2) sets the desired value to the control register (VL.sub.-- MODE) to select a processing content to be performed by a VLC processor (4). A local memory (7) is realized by a 4K-byte RAM to store retrieval tables used in decoding or encoding process. The sequence control section (5) controls a second DCT buffer section (11), an address generating section (12), a DCT generating section (14), VLC generating section (14), a shifter section (15), a VLC buffer section (16), and a VLC pack section (17), so that the process indicated by the control register (VL.sub.-- MODE) is executable.

Variable length code processor with encoding and/or decoding

A data retrieving apparatus comprising an address an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgment of said associative memory unit.

Taken storage apparatus using a hash memory and a cam

An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.

Pipeline processor with self timed data transfer

A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgement of said associative memory unit.

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Hyogo, Japan

Hisakazu Sato