Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hisakazu Kotani

Hironori Akamatsu

Shunichi Iwanari

Masashi Agata

Toshio Yamada

Hirohito Kikukawa

Akihiro Sawada

Tsutomu Fujita

Toru Iwata

Ichiro Nakao

Hiroyuki Yamauchi

Hiroshige Hirano

Naomi Miyake

Masahiro Ueminami

Motonobu Nishimura

Katsuhiko Shishido

Makoto Kojima

Akira Matsuzawa

Akinori Shibayama

Yoshiro Nakata

Kazuyoshi Nishi

Toshiaki Tsuji

Masanori Matsuura

Kazuyo Nishikawa

Toshikazu Suzuki

Junko Matsushima

Shoichiro Tada

A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

Semiconductor memory device and semiconductor device

In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Semiconductor memory device and transmission/reception system provided with the same

A first semiconductor chipincludes an integrated circuit formed on a face which is shown upwards in FIG.. A second semiconductor chipincludes an integrated circuit formed on a face which is shown downwards in FIG.. Between the first semiconductor chipand the second semiconductor chip, a non-conductive die padis interposed. The die padis provided with connection membersprotruding from the first semiconductor chipand the second semiconductor chip. The connection membersare plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chipand the integrated circuit on the second semiconductor chipare interconnected by two inter-chip connection wiresand, via the connection members. Thus, there is provided a semiconductor device composed of a plurality of internally connected semiconductor chips, such that the semiconductor device is easy to produce and requires a reduced number of component elements.

Semiconductor device

A semiconductor apparatus includes serially-connected bodies composed of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also included are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

Semiconductor apparatus including a switch element and resistance element connected in series

A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information. In erasing data, the redundancy control circuits switch the erasing bias circuits so as to inhibit the application of an erasing bias to word and source lines connected to control gates of the normal memory cell array that is replaced by the redundant memory cell array and also inhibit the erasing bias application to those connected to control gates of the unused redundant memory cell array.

Nonvolatile semiconductor memory device

A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Semiconductor memory, moving-picture storing memory, moving-picture

A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

Signal transmission driver circuit, receiver circuit, and method thereof

A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

Semiconductor integrated circuit having a plurality of chips

An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

Redundant memory cell selecting circuit having fuses coupled to memory

A semiconductor memory device according to the present invention includes a plurality of blocks. A plurality of first selection signals, second selection signals, and third selection signals are provided to the blocks. Each block includes: a memory cell array; a read/write circuit for simultaneously reading out a plurality of data from the memory cell array and subsequently simultaneously writing a plurality of further data into the memory cell array when the corresponding first selection signal is active; a parallel/serial conversion circuit for outputting the plurality of simultaneously read out data, the outputting being performed data by data in a serial manner along the time axis; a transfer gate for a reading operation controlled by the corresponding second selection signal, the gate outputting the plurality of data from the parallel/serial conversion circuit when the corresponding second selection signal is active; a serial/parallel conversion circuit for receiving the plurality of further data, the further data being sequential, and for outputting the plurality of sequential data to the read/write circuit in a parallel manner along the time axis; and a transfer gate for a writing operation controlled by the corresponding third selection signal, the gate outputting the plurality of sequential data to the serial/parallel conversion circuit when the corresponding third selection signal is active. Only one second selection signal is allowed to be active at a given time, while the other remain non-active. Only one third selection signal is allowed to be active at a given time, while the other remain non-active.

Semiconductor memory device having a plurality of blocks each including

In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Data transmission circuit, data line driving circuit, amplifying

When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

Growing community of inventors

Hyogo, Japan

Hisakazu Kotani