Kabushikikaisha Kenwood

Other

Nippon Hoso' Kyokai

Hisakazu Katoh

Akinori Hashimoto

Tomohiro Saito

Kenichi Shiraishi

Akihiro Horii

Fumiaki Minematsu

Shoji Matsuda

Soichi Shinjo

Hajime Matsumura

Shigeyuki Itoh

Junji Kumada

Kazuhiko Shibuya

Yuichi Iwadate

Shoji Tanaka

Toshihiro Nomoto

Kyoichi Saito

Hiroyuki Hamada

Kouichi Takano

Kohei Ueno

Hiroyuki Hamazumi

Masaru Takechi

Shoji Matuda

A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit , the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

Digital demodulator

After receiving a time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes, the received time division multiplex signal is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demodulated digital data signals is received correctly or not. When it is detected that a digital data signal transmitted by any one of the plurality of different transmission schemes is not received correctly, the relevant digital data signal is replaced by a suitable signal such as a null packet signal which does not affect a correct reception of the remaining digital data signals transmitted by the remaining transmission schemes to form a corrected time division multiplexed signal even if a digital data signal is not received correctly.

Digital data receiver

A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit ( ) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit ( ) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit ( ) calculates the polarity of the error frequency. A step frequency control circuit ( ) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.

Digital broadcasting receiver

A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter ( ), tuner and digital decoding portion ( ), an error correction code decoding portion ( ), a stream multiplexed signal separating portion ( ), an audio/video decoding portion ( ) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.

Digital broadcast receiving system for detecting short-breaks and holding information based on same

A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit ( ), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180&deg;, which are included in a carrier reproduction phase difference detecting circuit ( ), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit ( ) so that the phase obtained from the signal point position coincides with the phase convergence point.

Carrier reproduction circuit

A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.

Hierarchical transmission digital demodulator

A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter ( ) according to an inversion command signal &ldquo;0&rdquo; or &ldquo;1&rdquo; that is output from an inversion decision circuit ( ) depending on a BPSK signal of a known pattern. A phase error detector ( ) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter ( ). The phase error voltage is passed through a carrier filter ( ), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit . The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.

Synchronization acquiring circuit

An interleave frame is formed by combining slots corresponding to the same slot number in each frame when interleave process is performed in a super frame, and the data are read out along row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory.

Transmitter and receiver

Stabilized carrier recovery is achieved even at the time of a low C/N ratio by measuring the phase of a signal and controlling VCO or NCO (Numerical Controlled Oscillator) using only a period having few constellation points. At this time, false lock phenomenon is avoided as follows. That is, relatively short SYNC modulated by an already-known pattern is entered into a modulation wave, VCO or NCO oscillation frequency is swept in a wide range and sweep is stopped at a frequency in which the SYNC can be received, thereby carrying out coarse control AFC. Further, a period having long to some extent, having few constellation points is provided in the modulation wave and then, a difference between the frequency of a received modulated signal and a local oscillation signal of VCO or NCO is obtained in this period. This frequency difference is analyzed according to the phase differential function method, self-correlation function method or count method, and the VCO or NCO is controlled based on this result of analysis.

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Tokyo, Japan

Hisakazu Katoh