Hitachi, Ltd.

Hisakazu Date

Masatoshi Kawashima

Toyohito Ikeya

Masatoshi Ezawa

Masamichi Andou

A multiport switch circuit which performs transfer according to flow control and a protocol with an ordering rule specified, wherein the circuit for avoiding packets from clogging is realized in a small size. A packet receiving side circuit has a packet selection output circuit to suppress a circuit size by decreasing the number of transfer data paths, and the packet selection output circuit performs output of selected packets according to a priority packet type selection instruction signal in addition to output of a receiving order packet according to a receiving order output instruction signal to make it possible to avoid clogging caused because the packets made to wait for transmission by the flow control cannot be overtaken by another packet type according to the ordering rule.

Switching device

A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.

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Ome, Japan

Hisakazu Date