Fujitsu Corporation

Fujitsu Semiconductor Limited

Hisakatsu Yamaguchi

Hirotaka Tamura

Junji Ogawa

Kouichi Kanda

Kohtaroh Gotoh

Masaya Kibune

Shigetoshi Wakayama

Yasumoto Tomita

Satoshi Kawahara

Satoshi Matsubara

Sanroku Tsukamoto

Kozo Shimizu

Jun Matsui

Yoshiyasu Doi

Ali Sheikholeslami

Hideki Ishida

Shunichiro Masaki

Joshua Liang

An optical module switch device includes a first serial-parallel-converter coupled to first signal-lines coupled to optical modules, and second signal-lines, a number of the second signal-lines being greater than the first signal-lines thereof, and configured to transmit/receive first signals at a first transmission-rate to/from the optical modules by using the first signal-lines, respectively, a second serial-parallel-converter coupled to second signal-lines coupled to the first serial-parallel-converter, and third signal-lines, a number of the third lines being greater than the second signal-lines thereof, and configured to transmit/receive second signals at a second transmission-rate lower than the first transmission-rate to/from the first serial-parallel-converter by using the second signal-lines, respectively, and a switch circuit coupled to the third signal-lines, and configured to transmit/receive third signals at a third transmission-rate lower than the second transmission-rate to/from the second serial-parallel-converter by using the third signal-lines, respectively, to perform routing processing based on the received third signals.

Optical module switch device

A system includes the transmitter that transmits a first adjustment signal obtained based on a first parameter, detects, based on an output potential of the transmitter, a second parameter that is among values settable to the first parameter and sets the second parameter and the receiver that receives the first adjustment signal from the transmitter and acquire a second adjustment signal by adjusting the first adjustment signal based on a third parameter, sets the third parameter, counts the number of errors of the second adjustment signal based on a difference between the second adjustment signal and the test pattern, determines, based on the number of errors of the second adjustment signal, the second parameter to be set in the transmitter and controls the connection of the terminal resistor to the input terminal based on the second parameter.

Parameter setting transmission and reception system and parameter setting method

A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.

Jitter measurement circuit and jitter measurement system

A method includes transmitting a data signal generated by adjusting a phase of a data signal, receiving a control signal having a frequency lower than that of the data signal and used to control an apparatus of a transmission destination of the data signal, and applying, in a case where a signal level of the control signal is a level, jitter to the data signal by periodically changing a magnitude of an additional phase code to be added to a phase code representative of an adjustment amount for the phase but fixing, in a case where the signal level is a level different from the level, the additional phase code to 0, receiving the data signal and adjusting a phase of the data signal to generate a data signal and restoring the control signal from a phase code representative of an adjustment amount for the phase.

Control signal transmission and reception system and control signal transmission and reception method

A receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using two clocks having mutually-different phases do not match each other as an edge; and an adjustment circuit configured to perform an adjustment causing an internal clock frequency to be close to a data frequency in the received data based on a first probability that logics of third data in a next cycle of the first data and the second data match each other and a second probability that logics of fourth data in a next cycle of the second data and the third data match each other.

Receiving circuit and method for controlling frequency

A differential signal skew adjustment method includes: outputting a differential data signal including a first polarity signal and a second polarity signal from a transmission circuit in synchronization with a cycle of a reference clock; adjusting a phase of a detection clock obtained by dividing the reference clock in accordance with a phase of the first polarity signal; and adjusting a phase of the second polarity signal in accordance with an adjusted phase of the detection clock to adjust skew between the first polarity signal and the second polarity signal.

Differential signal skew adjustment method and transmission circuit

A clock phase interpolator includes: a phase interpolation processing circuit configured to generate an interpolated clock signal whose phase is interpolated from a plurality of operation clock signals having different phases; a band adjustment element coupled to the phase interpolation processing circuit, and configured to adjust an operational frequency band of the phase interpolation processing circuit by changing a setting value of itself; and a control circuit coupled to the phase interpolation processing circuit, and configured to detect a transition state for a reference clock signal of the interpolated clock signal, and configured to control the setting value of the band adjustment element on the basis of the detected transition state.

Clock phase interpolator, data transmission and reception circuit, and method of clock phase interpolation

To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.

Receiving device and receiving method

Receiving device

A first phase adjustment circuit adjusts phases of a data decision clock signal and a first boundary decision clock signal according to a phase adjustment amount based on an output signal of a data decision circuit and an output signal of a first boundary decision circuit. A second phase adjustment circuit adjusts a phase of a second boundary decision clock signal according to a result of adding the phase adjustment amount and a phase adjustment amount offset. An adaptive equalization control circuit adjusts an equalization coefficient of an equalization circuit according to a data width of an output signal of the equalization circuit based on a logical comparison result between the output signal of the data decision circuit and an output signal of a second boundary decision circuit when the phase adjustment amount offset is changed.

Receiver circuit

An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is &#xbd; unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Adaptive equalizer circuit

A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.

Clock recovery circuit and data receiving circuit

A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Phase interpolator for a timing signal generating circuit

A data transmission circuit that converts parallel data signals into a serial data signal to transmit the serial data signal includes a clock generation circuit, an output circuit, and a shift register circuit for securely conducting data communication among internal elements regardless of the improvement in data transfer rate, the increase in manufacturing variance, the variation in power supply voltage and temperature, and the like. The clock generation circuit generates a clock signal. The output circuit is provided to output the serial data signal. The shift register circuit acquires the parallel data signals and sequentially transfers the acquired parallel data signals to the output circuit in a bitwise manner with the use of a shift operation synchronized with the clock signal from the clock generation circuit.

Growing community of inventors

Kawasaki, Japan

Hisakatsu Yamaguchi