Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hisahiro Moriuchi

Toshifumi Takeda

Kenichi Kuroda

Akinori Matsuo

Masaki Shirai

Shoji Yoshida

Jiroh Sakaguchi

Satoshi Meguro

Isamu Kobayashi

Kouichi Nagasawa

Masahiro Ogata

Ryuuji Shibata

Kikuo Sakai

Youichi Matsumoto

Hideo Meguro

Takashi Sakamoto

Kanji Yoh

Yasuhiro Yoshii

Jinkichi Suto

Yoshibumi Ando

Sumiaki Takei

A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Semiconductor integrated circuit device

A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.

Floating gate FET with hydrogen barrier shield

A non-volatile memory element comprising a control gate formed by a diffusion layer, a floating gate comprising a conductive layer, the floating gate being partly overlapping with the control gate through a thin insulating layer, and a barrier layer formed to cover a part or the entire part of the floating gate is used as a defect remedy circuit for the memory circuit having read-only memory elements arranged in the form of a matrix for storing defective addresses corresponding to the word lines and bit lines and storing data corresponding thereto respectively.

Semiconductor memory device

A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

Read-only memory

An abnormal surge voltage such as frictional static electricity is often applied to the external terminals of a MOSIC. In the past, the output MOS transistor in the MOSIC during normal handling of the device frequently will have its gate insulating film broken down by the application of such an abnormal surge voltage to the drain thereof. In order to prevent the gate insulating film from being broken down, in this manner a resistor is connected between the gate of the output MOS transistor and a drive circuit for driving that output MOS transistor. This construction using a resistor is superior to the construction in which the voltage to be applied to the drain of the output MOS transistor is clamped by the use of suitable clamp means only because, with the resistor arrangement, the output characteristics of the MOSIC are not restricted.

Semiconductor integrated circuit device including a protective resistor

A semiconductor read-only memory is constructed of first and second read-only memories of the ratioless type each of which includes a plurality of MISFETs connected in series, and a logic circuit which logically combines output signals of the first and second read-only memories. When the output of the first read-only memory is to be determined by an input signal level thereof, the second read-only memory is forcibly brought into a precharge state. As a result, even when an undesirable coupling capacitor exists between an output terminal of the first read-only memory and an output terminal of the second read-only memory, the signal from the first read-only memory can be provided at the proper level.

Precharge for split array ratioless ROM

Growing community of inventors

Tanashi, Japan

Hisahiro Moriuchi