Hitachi, Ltd.

Renesas Technology Corp.

Hisahiko Abe

Keiichi Yoshizumi

Hisayuki Kato

Jun Tanaka

Kiyoshi Ogata

Kazuhiko Horikoshi

Kazufumi Suenaga

Hirofumi Tsuchiyama

Shinichi Nakabayashi

Shinji Nishihara

Yukio Kenbo

Yoshiteru Katsumura

Toshihiro Morisawa

Katsuhiro Ota

Toshihiro Nakajima

Masahito Yamazaki

Masaki Hiyama

Takashi Nishiguchi

Kosaku Tachikawa

Shinichi Nakabayshi

In a wafer polishing method, a within-wafer distribution model of a removal rate and a within-wafer distribution model of a polishing process are selected, and a within-wafer distribution of a removal rate is obtained by determining parameters of a within-wafer distribution model of a removal rate based on the within-wafer distribution of the film thickness before/after CMP, polishing condition data, and the selected within-wafer distribution model of the polishing process of the polished wafer. Then, a film thickness in the polishing process is estimated from passage of time based on the obtained within-wafer distribution of the removal rate, the selected within-wafer distribution model of the polishing process, and the film thickness before CMP of the wafer to be processed, thereby determining the polishing conditions with a restriction that the film thickness at each position in the within-wafer distribution of the film thickness after CMP satisfies the control limit.

Method of polishing semiconductor wafer

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device and manufacturing method thereof

In order to reduce micro scratches which tend to occur during chemical-mechanical polishing, a polishing slurry is diluted with deionized water immediately before it is supplied in a gap between a polishing pad and the surface of a wafer to be polished. By diluting the polishing slurry with deionized water to increase its volume, the concentration of coagulated particles contained in the polishing slurry can be lowered. For a mixture ratio of the polishing slurry and deionized water, about 1 (polishing slurry): 1&#x2013;1.2 (deionized water) is used, and the concentration of silica contained in the diluted polishing slurry is adjusted to about 3&#x2013;9 weight %, preferably about 4&#x2013;8 weight %, and more preferably about 8 weight %.

Fabrication method of semiconductor integrated circuit device

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of a crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device having ferroelectric film and manufacturing method thereof

For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface to be processed of individual wafers running through a mass-production process so as to suppress occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a condition filled in a container for at least 30 days or over, preferably 40 days or over, and more preferably 50 days or over so that the concentration of coagulated particles having a size of 1 &mgr;m or over is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.

Fabrication method for semiconductor integrated circuit device

In the manufacturing method, micro scratches are detected without performing a breakdown inspection on wafers flowing through a mass production process. The method comprises: forming an insulating film on main surfaces of a plurality of first wafers which flow through a mass-production process; preparing a dummy wafer for monitoring, on which a silicon-oxide-based insulating film is formed; performing chemical mechanical polishing on the insulating films respectively formed on main surfaces of the plurality of first wafers and the dummy wafer; performing etching on the insulating film of the dummy wafer with use of a solution containing hydrofluoric acid, after the step of performing the chemical mechanical polishing; and measuring a number of scratches on the insulating film of the dummy wafer subjected to the etching.

Semiconductor integrated circuit device manufacturing method including chemical mechanical polishing, and detection and evaluation of microscratches caused thereby

In order to improve the dielectric constant, residual dielectric polarization, hysteresis characteristics, etc. of a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM, a target having a density of at least 90% of the theoretical value is used in forming, by sputtering, a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM.

Process for producing semiconductor integrated circuit device

Growing community of inventors

Mito, Japan

Hisahiko Abe