Sony Corporation

Hisafumi Motoe

Masaharu Tokuhara

Hiroyuki Kawashima

Yukinori Gengintani

Masami Ogata

Seiji Kimura

Masayuki Hongu

Takaya Hoshino

Toshio Sarugaku

Yosuke Yamamoto

A noise reduction method for reducing noise in an input video signal to output an output video signal includes the steps of generating a motion-compensated reference video signal from the output video signal; delaying the output video signal to generate a non-motion-compensated reference video signal; mixing the motion-compensated reference video signal with the non-motion-compensated reference video signal to generate a reference video signal; subtracting the generated reference video signal from the input video signal to generate a differential signal; compensating the differential signal to generate a noise reduction signal; and subtracting the noise reduction signal from the input video signal.

Noise reduction method, noise reduction program, recording medium having noise reduction program recorded thereon, and noise reduction apparatus

The present invention is related to a video signal processing apparatus and method, a recording medium, and a program which are suitably for use in determining whether an input video signal is standard or nonstandard. In synchronization with the edge of an advance vertical sync signal xAVD, a free-running vertical sync edge counterincrements by 1 the count value which cycles between 0 through 7 and outputs the count value to a free-running field ID edge counterand a comparator. In synchronization with the rising and falling edges of a field ID signal AFD, the free-running field ID edge counterincrements the count value by 1. The comparatorgenerates a nonstandard signal detection signal in correspondence with the FD edge count value with the V count value being 7 and a vertical sync signal xVD being at L level. The present invention is applicable to TV receivers for example.

Video signal processing device and method, recording medium, and program

The present invention relates to a video signal processing device for avoiding a phenomenon that noise is upwardly or downwardly shifted due to noise reducing operation when a non-standard signal is input. When a non-standard signal is input as an input video signal, coefficients of interpolating filters for carrying out interpolation on pixels of timely-sequential field video signals are fixed as a non-standard signal supporting signal processing. With this processing, interpolated pixels achieved by the interpolation processing are located at the same vertical spatial position, and pixels which are noise-reduced by the interpolated pixels are located at the same vertical spatial position as pixels before original noise is reduced, thereby locating the pixels at the same horizontal position.

Video signal processor and video signal processing method

Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal in a given field, the next succeeding scan line signal in that field, an interlaced scan line signal in the next succeeding field and an interlaced scan line signal in the next preceding field. A first combining circuit combines the signal values of the next succeeding field interlaced scan line signal and the next preceding field interlaced scan line signal to form a first combined scan line signal. A second combining circuit combines the signal values of the first scan line signal in the given field and the next succeeding scan line signal in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal intermediate successive main scan lines in the given field.

Interpolation of scan lines from video signals having interlaced scan

A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit amount circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.

Time-division bit number conversion circuit

A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

Adaptive comb filter circuit including a plurality of filters and a

A signal processing circuit for a moving detection circuit which has a coefficient generator which is connected to an output of a moving detection circuit. A level comparator is connected between the moving detection circuit and the coefficient generator and is also connected to a threshold voltage switch. An isolated-point eliminating circuit is connected between the level comparator and a time base filter which is connected at its output terminal to the input terminal of the coefficient generator. The coefficient generator includes a plurality of one bit delay devices which are connected in series and the plurality of one bit delay devices have a plurality of output terminals, and an adder is connected to the plurality of output terminals so as to add the output signals.

Signal processing circuit for a moving detection circuit which includes

In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.

Growing community of inventors

Tokyo, Japan

Hisafumi Motoe