Hitachi, Ltd.

Other

Hisae Yamamura

Toshifumi Honda

Takanori Ninomiya

Yukio Matsuyama

Yuji Takagi

Hideaki Sasazawa

Hideaki Doi

Hirohito Okuda

Makoto Saeki

Ludwig Listl

Kiyoshi Nagai

Takeshi Fukazawa

Shigeshi Yoshinaga

Tadashi Abe

With a view to providing a monitoring system for the quality and manufacturing conditions of electronic circuits capable of facilitating the grasping of correlation's between diverse manufacturing conditions and manufacturing states, statistically characteristic images are selected out of a group of images retrieved from a detection information database by specifying at least one out of the values of feature quantities, design information and manufacturing conditions, and are displayed.

Method monitoring a quality of electronic circuits and its manufacturing condition and system for it

A defect judgement processing method and apparatus which can optimize image processing and defect judgement parameters for a detection image cut out by each inspection window to avoid erroneous judgement and defect missing and to realize reliable defect judgement. An image data generator cuts out ranges indicated by a plurality of predesignated inspection windows from a detected image and stores them in a memory, a window data generator generates window data having inspection conditions attached thereto with respect to the plurality of inspection windows and stores them in the memory, a feature extractor reads out detection images of the ranges indicated by the inspection windows from the memory and extracts a structural feature parameter therefrom on the basis of an image processing parameter conforming to the inspection condition obtained by the window data, and a defect judger performs its defect judging operation over the extracted structural feature parameter on the basis of a defect judgement parameter conforming to the inspection condition.

Defect judgement processing method and apparatus

A method for automatic focusing and three dimensional profile detection and an apparatus for automatic focusing and three dimensional profile detection have the purpose of detecting a three dimensional profile of the state of mounting of parts or soldering on a board without the affects of warp, even if the board of the detection object is warped, as if the surface of the board were on a flat plane. The board surface height is detected in a plurality of windows corresponding to stage scanning regions from a three dimensional profile signal of the part-mounted board detected by a height detection optical system. The board height or inclination in the next window is forecasted from the board surface height and the control history of stage height in the already-detected plurality of windows. Based on the forecasted board surface height or inclination, the speed or height in the Z direction of a Z-stage is controlled according to a feedforward method with scanning so as that the board surface and the focal plane of the height detection optical system are made coincident.

Method and apparatus for automatic focusing and a method and apparatus

A measuring method and apparatus for automatically and accurately measuring the sizes of portions of a hybrid integrated circuit chip and circuit patterns formed thereon or a wiring board and wiring patterns formed thereon. An image of a portion of a hybrid integrated circuit chip or wiring board is obtained through a TV camera which provides image signals representing images including those of objective portions. The image signals are processed to calculate the positions of the objective portions automatically. The size of an arbitrary objective portion is determined from a difference between respective positions of other objective portions.

Method and apparatus for measuring the size of a circuit or wiring

In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.

Semiconductor memory device having redundancy memory cells for replacing

Growing community of inventors

Yokohama, Japan

Hisae Yamamura