Matsushita Electric Industrial Co., Ltd.

Kabushiki Kaisha Toshiba

Matsushta Electric Co., Ltd.

Hiroyuki Yamauchi

Toru Iwata

Hironori Akamatsu

Yutaka Terada

Satoshi Takahashi

Takashi Hirata

Tadahiro Yoshida

Toshio Yamada

Keiichi Kusumoto

Yoshihide Komatsu

Yukio Arima

Masashi Agata

Hideo Asaka

Masahiko Yamada

Takefumi Yoshikawa

Hisakazu Kotani

Tsuneji Kameda

Seiji Fujiwara

Kazuo Itoh

Akihiro Sawada

Hisao Watanabe

Masafumi Komai

Yuko Kawajiri

Yasuo Takagi

Akira Matsuzawa

Shunichi Iwanari

Michihiro Inoue

Katsuji Satomi

Hirohito Kikukawa

Atsushi Fujiwara

Motoyoshi Iwata

Tetsuyuki Fukushima

Masato Yoshino

Kazuhiro Matsuyama

Shigeo Kasai

Hiroyasu Takehara

Takatoshi Asada

Shoichiro Tada

Ryoji Yoshimura

Yoshinori Yamagami

Atsuhi Fujiwara

A hydrogen production system that achieves a highly-efficient hydrogen production operation even when a time-varying electric power source is used is provided. A hydrogen production system includes a capacitor inputting electric power energy from a renewable power supply, and storing electric power, a pulse voltage generation unit generating a pulse voltage having a set amplitude and a set cyclic period by using the electric power stored in the capacitor, and an electrolytic cell applying the generated pulse voltage, and generating hydrogen by high temperature steam electrolysis by using steam supplied into the electrolytic cell.

Hydrogen production system and method for producing hydrogen

A hydrogen production system that achieves highly-efficient hydrogen production even when hydrogen is produced by using the plurality of cell stacks is provided. A hydrogen production system includes a plurality of cell stacks provided within a reaction containment, the cell stacks generating hydrogen by high temperature steam electrolysis by supplying steam to the plurality of cell stacks, a first flow path guiding the steam to each of the cell stacks, a second flow path causing a carrier gas containing air as a main component to flow into the reaction containment, and a flow regulation device provided at an inlet of the steam in each of the cell stacks, the flow regulation device regulating a flow rate of the steam caused to flow into each of the cell stacks to be uniform.

There are provided an RF power amplifier transistor (), a bias supply circuit () which supplies a bias current to the base of the RF power amplifier transistor and a bias control circuit () connected between the base of the RF power amplifier transistor and bias supply circuit, and the bias control circuit is connected to the power supply () of the RF power amplifier transistor, thus realizing high efficiency of the RF power amplifier when the power level is low and improving the temperature characteristic of the power amplifier when the power level is low.

Radio frequency power amplifier

A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS transistors in the ROM region and channel regions of access transistors in the SRAM region have substantially the same p-type impurity concentration. Accordingly, the threshold voltages of the transistors are adjusted by making use of the great dependence of the threshold voltage of the transistor on the channel width.

Semiconductor integrated circuit device and method for manufacturing the same

A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

Semiconductor integrated circuit device and method for designing the same

A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.

Mask ROM

A semiconductor system includes a plurality of memory systems (SARM, ROM, etc.) and circuit systems. The semiconductor system further includes an analog power supply circuit which is common to the memory systems. The analog power supply circuit supplies a source potential to word line drivers of the memory systems. The source potential is set to a potential different from a ground potential and a supply voltage of the semiconductor system.

Semiconductor system having a source potential supply section

A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a physical address based on a correspondence between an address space and the plurality of memory regions. The correspondence is defined based on an inherent condition regarding a performance of the memory.

Memory system

A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

Clock recovery circuit

First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

Semiconductor integrated circuit and method for fabricating the same

A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

Signal transmitting receiving apparatus

A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.

Method for fabricating semiconductor integrated circuit device

In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

SRAM device

In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.

SIGNAL TRANSMITTING CIRCUIT, SIGNAL RECEIVING CIRCUIT, SIGNAL TRANSMITTING/RECEIVING CIRCUIT, SIGNAL TRANSMITTING METHOD, SIGNAL RECEIVING METHOD, SIGNAL TRANSMITTING/RECEIVING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL METHOD THEREOF

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Osaka, Japan

Hiroyuki Yamauchi