Nippondenso Co., Ltd.

Denso Corporation

Hiroyuki Yamane

Yasushi Higuchi

Yoshihiko Isobe

Tetsuo Fujii

Mitsutaka Katada

Takeshi Yamauchi

Kazuo Akamatsu

Noriyuki Iwamori

Atsushi Komura

Takeshi Kuzuhara

Tsutomu Kawaguchi

Ryoichi Kubokoya

Tooru Yamaoka

A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cmor less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

Method of manufacturing semiconductor device

A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime

The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film , a titanium layer , a titanium nitride layer that serves as the barrier layer, an aluminum alloy wiring layer and a protective film are formed on top of the silicon substrate to compose the electrode structure. In this case, a distortion relaxation layer , with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer and the aluminum alloy wiring layer . Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.

Electrode for semiconductor device and method for manufacturing same

A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Semiconductor device and fabrication process thereof

The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.

Electrode for semiconductor device including an alloy wiring layer for

Enhancement-type semiconductor having reduced leakage current

A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved. A method of manufacturing a CMOS having such a MIS transistor decreases the number of the manufacturing steps because the double offset region of a first conductivity type channel MIS transistor and the offset region of a second conductivity type channel MIS transistor are simultaneously formed.

Method of manufacturing a complementary MIS transistor

A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.

High withstanding voltage MIS transistor

A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type well regions are covered with an insulating film on which gate electrodes are formed in a predetermined pattern by means of a photo-resist. This photo-resist is used as a channelling block layer when an N type impurity is implanted into the P type well region near the gate electrode so as to form an N type diffusion layer. As a result, the photo-resist prevents the N type impurity from channelling into the gate electrode so that a leak current does not occur within the P type well region of the N type channel transistor.

Method of producing a complementary-type semiconductor device

A method of manufacturing a semiconductor apparatus having a plurality of elements formed on a substrate comprises forming a pad oxidized film on the surface of the semiconductor substrate, forming a pattern of silicon nitride film to coat device areas on the pad oxidized film, and injecting boron ions into that surface of the pad oxidized film where no silicon nitride film is present, thereby to form a channel stopper region. Using the pattern of the silicon nitride film as a mask, a heat oxidized film is then formed on an elements separating region by heat oxidization, and ions of Si, N, C, or the like are injected into the surface of the heat oxidized film with such an acceleration energy that the ions are not injected into the silicon nitride film thereby to change the quality of the heat oxidized film. The silicon nitride film is removed by etching and the heat oxidized film is etching-treated by a solution of the hydrofluoric acid group to etching-remove particularly the bird's beak portions each of which is present along and under the peripheral rim of an element area of the silicon nitride film.

Method of manufacturing a semiconductor device having a plurality of

In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.

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Anjo, Japan

Hiroyuki Yamane