Canon Kabushiki Kaisha

Ntt Docomo, Inc.

Fujitsu Corporation

Kioxia Corporation

Other

Honda Motor Co., Ltd.

Nippon Telegraph and Telephone Corporation

Unisia Jecs Corporation

Kanto Kagaku Kabushiki Kaisha

Hitachi, Ltd.

Meiji Seika Kaisha, Ltd.

Kokusai Denki Kabushiki Kaisha

Hiroyuki Yamaguchi

Mitsuru Kobayashi

Satoru Adachi

Minoru Etoh

Sadaatsu Kato

Kazuo Sugimoto

Shunichi Sekiguchi

Takashi Maeda

Hideki Takahashi

Hideho Inagawa

Hideaki Katayama

Shoji Matsumoto

Juichi Arai

Masafumi Kamei

Masaru Kato

Tsunao Hombo

Takashi Numagi

Daishiro Sekijima

Yuta Kojima

Ryoichi Kato

Atsushi Okamoto

Hajime Yamazaki

Fumiyuki Yamaoka

Mitsuo Sasaki

Hiroki Matsudaira

Hirokazu Takeuchi

Shinjiro Umetsu

Nobuaki Yamashita

Yusuke Murai

Takahiro Miomo

Masato Ota

Takeshi Fuchida

Toshiyasu Takasugi

Yasuhiro Ogiri

Youhei Tazawa

Takehiko Tsutsumi

Tatsuaki Sekigawa

Hiroshi Arakawa

Kazushige Sakoh

Naomi Yokoyama

Kenichi Abe

Chikako Murakami

Toshihiro Kikkoji

Hiroyuki Nago

Toshiaki Takezawa

Mineo Shoman

Koji Fukuda

Shin′ichi Nishimura

Ayumi Oshikata

Shin'ichi Nishimura

Hiroyuki Kuroyama

Tomoya Sawaguchi

Shigeru Meiji Seika Kaisha Ltd Chikase

Yukiko Meiji Seika Kaisha Ltd Yokoi

A DC/DC converter includes: multiple channels each including a switching circuit and an inductor; an output line having one end connected to the other end of the inductors of the multiple channels and the other end connected to a load; and a controller. The multiple channels include first to third channels, and the inductors of the first and second channels have a larger inductance value than the inductor of the third channel. When current flowing in the load is first current, the controller controls the switching circuits so that only the first channel is activated; and when the current flowing in the load is second current that is larger than the first current, the controller controls the switching circuits so that the first and second channels are operated in-phase and the third channel is operated in a phase different from the phase of the first and second channels.

DC/DC converter, electronic module, and electronic apparatus

A memory controller specifies, from a nonvolatile memory, a final page candidate, which is a candidate to be the physical page to which data is last written in a logical block. The memory controller executes an upward check process to determine whether the number of programmed physical pages is among a first range number of physical pages in a reverse order from the final page candidate is equal to or greater than a first reference value. The memory controller executes a downward check process determining whether the number of programmed physical pages is among a second range number of physical pages existing in the downward order from the final page candidate is equal to or less than a second reference value, and specifies the physical page to which data is last written in the logical block from results of the upward check process and the downward check process.

Memory system and control method thereof

A ground fault detection device connected to a high-voltage battery and a positive electrode side Y capacitor includes a detection capacitor operating as a flying capacitor and a discharge circuit including at least a fifth switch. A one end of the discharge circuit is connected to a first circuit that connects a positive electrode side of the high-voltage battery and a one end of the detection capacitor. An another end of the discharge circuit is connected to a second circuit that connects an another end of the detection capacitor and a ground.

Ground fault detection device

A ground fault detection device connected to a high-voltage battery and a positive electrode side Y capacitor includes: a detection capacitor operating as a flying capacitor, a first switch and a first resistor connecting a positive electrode side of the high-voltage battery and one end of the detection capacitor in series, and a discharge circuit including at least a discharge capacitor. The discharging circuit has one end connected to the positive electrode side of the high-voltage battery and an another end connected to the negative electrode side of the high-voltage battery. The discharge circuit further includes: a fifth switch that connects one end of the discharge capacitor and the positive electrode side Y capacitor, and a second discharge resistor and an eighth switch that connect the another end of the discharge capacitor and the ground in series.

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.

A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

Memory system configured with a synthesized logical block into which a plurality of data units forming an error correction frame are written

A dried vitrigel membrane is produced by a method including the following steps of (1) a step of keeping a hydrogel in the inside of a wall surface mold with a shape the same as the desired shape disposed on a substrate, and discharging a part of free water within the hydrogel from a gap between the substrate and the wall surface mold; (2) a step of removing the wall surface mold from the top of the substrate; (3) a step of drying the hydrogel to remove the residual free water, thereby fabricating a vitrified dried hydrogel; (4) a step of rehydrating the dried hydrogel to fabricate a vitrigel membrane; and (5) a step of redrying the vitrigel membrane to remove free water, thereby fabricating a vitrified dried vitrigel membrane.

Dried hydrogel, dried vitrigel membrane, and methods for producing the same

A printed wiring board includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings each include a first via conductor disposed outside a first region, a second region, and a third region in a plan view, and a first conductor pattern extending from the first via conductor to the first region. The plurality of second wirings each include a second via conductor disposed outside the first region, the second region, and the third region, and a second conductor pattern extending from the second via conductor to the first region. A fourth region overlaps with a fifth region in the plan view, the fourth region being a region in which a plurality of first conductor patterns are disposed, the fifth region being a region in which a plurality of second conductor patterns are disposed.

Printed circuit board, printed wiring board, electronic device, and camera

First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.

Printed circuit board

A printed circuit board (e.g.,) includes capacitor elements (e.g.,and). The capacitor element (e.g.,) returns a common mode current included in a signal output from a signal output terminal (e.g.,) of a semiconductor element (e.g.,), to a ground terminal (e.g.,) of the semiconductor element (e.g.,). The capacitor element (e.g.,) returns a common mode current included in a signal output from a signal output terminal (e.g.,) of the semiconductor element (e.g.,), to the ground terminal (e.g.,) of the semiconductor element (e.g.,). The capacitor elements (e.g.,and) are arranged such that the mutual inductance between a parasitic inductance of the capacitor element (e.g.,) and a parasitic inductance of the capacitor element (e.g.,) for the common mode currents is a negative value. Accordingly, the effective inductances of the first and second capacitor elements for the common mode currents are reduced, which suppresses radiation noise.

A job assignment apparatus includes: a correlation calculation unit to calculate a correlation between an execution time used for processing a program that depends on a computer resource operating at the start of an execution request job and an execution time used for processing a predetermined amount of data in the execution request job which operates immediately after completion of an operation of the program; a resource identification unit to identify the computer resource on which the execution request job depends on the basis of the correlation calculated by the correlation calculation unit; and a job assignment unit to assign the execution request job to one of execution servers connected to the job assignment apparatus so as to exclude simultaneous execution of a job that depends on the same computer resource as the computer resource identified by the resource identification unit and the execution request job.

Batch job assignment apparatus, program, and method that balances processing across execution servers based on execution times

A virtual machine managing program manages plural physical machines and makes a computer device execute processing through virtual machines developed on each physical machine. Virtual machines are assigned to physical machines on the basis of CPU usage rate and temperature, and are moved among the physical machines as needed, to maintain acceptable operating conditions.

Recording medium having virtual machine managing program recorded therein and managing server device

A virtual machine managing method includes: a dependence relation list generation step of detecting a dependence relation among virtual machines implemented on a physical machine and generating a dependence relation list, based on a detection result; a target management table generation step of reading, when a selection instruction for selecting a target virtual machine to be halted among the plurality of implemented virtual machines is detected; and a halted target presentation step of reading the virtual machine identification information on all of the virtual machines in dependence relation with the target virtual machine to be halted, and visually presenting the read virtual machine identification information on all of the target virtual machines to be halted.

Recording medium recording thereon virtual machine management program, management server device, and method for managing virtual machine

A variable-length encoder that feeds a Coded Block Pattern (CBP) as an input symbol to variable-length code output part. Coded symbol memory supplies CBPs in neighboring blocks as coding map table reference information to coding map table provider. Coding map table provider determines a coding map table used in coding of the CBP, based on these CBPs in the neighboring blocks, and provides a coding map table Hto variable-length code output part. Variable-length coding table provider feeds a variable-length coding table to variable-length code output part. Then the coding target CBP is subjected to variable-length coding, and the resultant is outputted as coded data. This allows information source coding of coding symbols to be performed efficiently according to the coding condition and the property of image.

Image encoding apparatus, image decoding apparatus, image encoding method, image decoding method, image encoding program, and image decoding program

Growing community of inventors

Yokohama, Japan

Hiroyuki Yamaguchi