Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroyuki Yabuno

Makoto Usui

Yuji Takagi

Machiko Satou

Yoshihisa Fukushima

Yoshikazu Yamamoto

Takashi Yumiba

Hironori Deguchi

Kenji Takauchi

Toshinori Maeda

Takahiro Ichikura

Syuji Matsuda

Hidenori Akiyama

When recording is carried out in a DVD-RAM, if at least one address mark could have been detected at the header section, after a test light emission for a laser power control is carried out at a GAP section, normal recording is carried out from GUARD1. Herein, if the delay time in the reproduced data would have increased, and if the head of the GAP section has been passed by at the timing when the AM4 is detected in a period during judging whether the fourth AM has been detected or not, it would not be possible to carry out a test light emission normally at the GAP section. In an optical disc recording device of the present invention, when any of the first to third address marks could have been detected, a test light emission is carried out at the GAP section as conventional, and normal recording is carried out from GUARD1 with controlling the laser powers on the basis of that result. When only AM4 could have been detected, the test light emission is not carried out and normal recording from GUARD1 is carried out.

Optical disc recording device and optical disc recording system

A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes. The second error correcting codes have the same number of corrections as the first error correcting codes. A code length of the second error correcting codes is shorter than a code length of the first error correcting codes.

Data recording method, recording medium and reproduction apparatus

In an error detection method of the present invention, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arrangement are subjected to a first error detection code operation while correcting the inter-data continuity by skipping the data so that the arrangement of the code strings have continuity. Then, error data positions and error data numerical values of the target code strings are calculated on the basis of a syndrome obtained in the syndrome operation, and only the error data position among the target code strings are subjected to a second error detection code operation again on the basis of the error data positions and the error data numerical values. Using the operation result, the operation result by the first error detection code operation is updated, thereby simultaneously performing ECC processing and EDC processing for the target code strings which are inputted in a discontinuous arrangement.

Error detection device and error detection method

The present invention provides a CPU-containing LSI in which software stored in an external memory is incorporated partially into a RAM and thereby the capacity of the RAM to be used can be held down, and an optical disk device including the same. In the CPU-containing LSI, the RAM includes a software storage region where software read in from the external memory on a module-by-module basis is stored, and an entry table in which entries are stored, with the entries each containing at least information as to a location and a size of a module stored in the software storage region. The CPU refers to the entry table to decide the location where a module to be read in from the external memory to the software storage region is to be stored, according to an incorporation-location search program.

CPU-containing LSI, and optical disk device and LSI device with the same

A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (A), a DSV change amount calculator () calculates change amounts (&#x394;DSVa, &#x394;DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (). A modulated code determinator () compares the change amounts (&#x394;DSVa, &#x394;DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector () selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (), and outputs the selected code as a modulated code (CODE) for source data (DATA).

Digital modulation apparatus and digital modulation method

A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, and second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability. The second error correcting codes have a second correction capability higher than the first correction capability. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes. The first and second error correcting codes are encoded using Reed-Solomon codes.

A recording medium is provided for storing a data stream containing first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability, and the second error correcting codes have a second correction capability higher than the first correction capability. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes. The second information includes address information.

The present invention provides a central processing unit-containing large-scale integration (hereinafter, referred to as a 'CPU-containing LSI') in which software stored in an external memory is incorporated partially into a random access memory (hereinafter, referred to as 'RAM') and thereby the capacity of the RAM to be used can be held down, and an optical disk device including the same. In the CPU-containing LSI, the RAM includes a software storage region where software read in from the external memory on a module-by-module basis is stored, and an entry table in which entries are stored, with the entries each containing at least information as to a location and a size of a module stored in the software storage region. The CPU refers to the entry table to decide the location where a module to be read in from the external memory to the software storage region is to be stored, according to an incorporation-location search program.

An information recording medium includes a plurality of modulated data areas for recording a plurality of modulated codes; and a plurality of SYNC code areas for recording a plurality of SYNC codes. Data other than the plurality of modulated codes is recorded in at least one of the plurality of SYNC code areas in the form of at least one SYNC code.

Information recording medium, information recording apparatus, information recording method, information reproduction apparatus and information reproduction method

A data recording method comprising the steps of encoding user data into first error correcting codes having a first correction capability, encoding control information into second error correcting codes having a second correction capability higher than the first correction capability, generating a data stream containing the first error correcting code, the second error correcting code, and synchronization signals, wherein the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes, and recording the data stream.

An information recording and reproduction apparatus includes a data transfer controller for receiving data to be written transferred from a host computer; a cache data memory divided into a plurality of segments for temporarily storing the data to be written received by the data transfer controller; a segment connection information memory for storing segment connection information representing a logical connection state of the plurality of segments; a buffer memory controller for managing the data to be written temporarily stored in the cache data memory; and a recording and reproduction controller for writing the data to be written temporarily stored in the cache data memory into a recording medium. The buffer memory controller updates the segment connection information so as to change the logical connection state of the plurality of segments.

Information recording and reproduction apparatus

An error-detecting information adding apparatus transfers original data received from an external host apparatus to a memory and to an error-detecting code generating unit in one DMA transfer so that while the original data is transferred to the memory, an error-detecting code is generated. The error-detecting code generated by the error-detecting code generating unit is transferred from the error-detecting code generating unit to the memory.

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Osaka, Japan

Hiroyuki Yabuno