Fujitsu Corporation

Hiroyuki Utsumi

Yoshio Hirose

Yasuhiro Yamazaki

Toshiaki Saruwatari

Hitoshi Yoda

Taizoh Satoh

Hideyuki Iino

Ken Ryu

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Bus control system for integrated circuit device with improved bus access efficiency

The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST signal. The first area is not initialized if the second reset signal is generated. The first and second areas are not initialized if the third reset signal is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized.

Method and processor for initializing a plurality of non-overlapping areas with associated flags and signals

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

An OR circuit () OR-operates an emulator reset signal () based on a reset instruction from an emulator () and an external reset signal () supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor () and a companion chip () as a system reset signal (), thereby initializing both chips of the processor () and the companion chip () in accordance with the reset the emulator ().

Reset control system and method

A microprocessor includes a register and a comparator. The register stores an address area, the address area requiring a guarantee of an access order. The comparator compares an address of the address area held in said register with an address of an address area indicated in an access request from CPU, and outputs a signal to execute an access request succeeding the access request from the CPU after executing an access request preceding the access request from the CPU when the address area indicated in the access request from the CPU matches the address area held in said register.

Microprocessor executing a program to guarantee an access order

The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.

Data processor having instruction cache with low power consumption

A command fetch control section has an address selection function of selecting the start address of an initialization program stored in a local memory (RAM ) or an external memory (ROM ) connected through external buses and , based on an address selection signal MS externally given. When a processor in which one or both of the supplies of its internal clocks and have been stopped after the system wad powered on, is to be restarted, the processor can read out the initialization program necessary for its restarting operation from the high-speed RAM . Thus the restarting operation can be performed rapidly.

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Kawasaki, Japan

Hiroyuki Utsumi