Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Renesas Technology Corp.

Matsushita Electronics Corporation

Hiroyuki Umimoto

Shinji Odanaka

Kaori Akamatsu

Masafumi Tsutsui

Shin Hashimoto

Kyoji Yamashita

Masahiro Imade

Takato Handa

Tatsuya Kunikiyo

Katsumi Eikyu

Taiji Noda

Satoe Miyata

Tadashi Kadowaki

Mutsumi Kobayashi

Katsuhiro Ohtani

Hisashi Ogawa

Tetsuya Ueda

Shinichi Imai

Kousaku Yano

Michikazu Matsumoto

Hiroaki Nakaoka

Susumu Akamatsu

Susumu Matsumoto

Kazumi Kurimoto

Masanori Fukumoto

Yasuo Mizuno

Yuka Terai

Atsuhiro Kajiya

Kentaro Nakanishi

A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

Method of manufacturing a semiconductor device including a stress film

Semiconductor device including a stress film

Semiconductor device including MISFET having internal stress film

Semiconductor device having internal stress film

An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

Semiconductor device and method for fabricating the same

A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

Semiconductor device including a MISFET and a MIS capacitor

A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

Method for fabricating a semiconductor device having a pocket dopant diffused layer

As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

A substrateconsists of a semiconductor layeras an element formation region and an STIas an isolation region. A gate dielectricis provided on the semiconductor layer, and a gate electrodeis provided to extend from the top of the gate dielectricto the top of the STI. A sidewallfor covering the sides of the gate electrodeis provided to extend across the top of the semiconductor layerto the tops of regions of the STIadjacent to the outer edges of the semiconductor layer. The sidewallis employed as an ion implantation mask for forming high-concentration impurity diffusion layerseach serving as a source/drain region.

A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Semiconductor device and method of fabricating the same

A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages Vand V, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Semiconductor device and capacitance measurement method

It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions () and (') are selectively formed in a surface of a body region (), and extension regions () and (&#x2032;) are extended from tip portions of the source-drain regions () and (&#x2032;) opposed to each other, respectively. A gate insulating filmis formed between the source-drain regions () and (&#x2032;) including the extension regions () and (&#x2032;) and a gate electrode () is formed on the gate insulating film (). A region corresponding to a pocket region(&#x2032;) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region(&#x2032;) and a peripheral portion of the extension region ().

Semiconductor device and method of checking semiconductor storage device

A hard mask which has an opening for exposing a p-type region defined in a silicon substrate and is made of, for example, a BPSG film is formed. Then, the hard mask is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask as a mask, thereby forming an n layer having an LDD structure. Thereafter, the implantation hard mask is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

Method for fabricating a semiconductor device including using a hard mask or a silylated photoresist for an angled tilted ion implant

In a semiconductor device according to the present invention, an n-type MISFET including a semiconductor substrate , a source region , a drain region and a gate electrode is provided. On the semiconductor substrate , a first interlevel insulating film covering the MISFET , a second interlevel insulating film and third interlevel insulating film are provided. On the first interlevel insulating film , a first gate interconnect for electrically connecting a gate electrode and the outside, a first drain interconnect for electrically connecting the drain region and the outside are provided so as to face each other with part of a second interlevel insulating film interposed therebetween.

Growing community of inventors

Hyogo, Japan

Hiroyuki Umimoto