Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroyuki Tsujikawa

Kenji Shimazaki

Shouzou Hirano

Kiyohito Mukai

Hidenori Shibata

Mitsumi Ito

Masatoshi Sawada

Shinichi Kimura

Junichi Shimada

Hiroshi Benno

Takashi Mizokawa

Junko Honma

Seijiro Kojima

Seijirou Kojima

Chihiro Hyoto

Kiyoshi Mukai

Tatsuo Ohhashi

Mitsumi Itoh

Kazuhiro Sato

Masao Takahashi

Takahiro Ichinomiya

Shinya Tokunaga

Masanori Tsutsumi

Hisato Yoshida

Tadashi Tanimoto

Shozo Hirano

Kasumi Hamaguchi

Hidetoshi Narahara

Kaori Matsui

Ritsuko Kurazono

It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device

Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device

An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Design method for semiconductor integrated circuit suppressing power supply noise

To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high. A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device

A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.

Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method

To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized. Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device

In a gate-level logic simulation, a change in electric current is calculated from event informationoutput from a logic simulatorthrough use of a current waveform calculation section. The thus-calculated change in current is subjected to FFT processing through use of an FFT processing section, thereby determining a frequency characteristic of EMI and enabling EMI analysis.

Method of analyzing electromagnetic interference

In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of 'the Static timing analysis technique'. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.

A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.

Interconnection structure and method for designing the same

A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.

Method and apparatus for analyzing electromagnetic interference

An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method

A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.

Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interference

A method of analyzing an electromagnetic interference amount of an LSI includes an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.

Electromagnetic interference analysis method and apparatus

With respect to layout data of a semiconductor integrated circuit, a latch-up verifying operation is carried out in high precision. In a latch-up verifying method, a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information.

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Shiga, Japan

Hiroyuki Tsujikawa