Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Hiroyuki Tsuda

Takayuki Suzuki

Tomonori Kamiya

Masayuki Ishibashi

Takeshi Kura

Hiroki Nagai

Kaneo Watanabe

A first terminal supplies the bias voltage to a high-potential-side input terminal of a hall element. A second terminal supplies the ground potential to a low-potential-side input terminal of the hall element. A P-channel type transistor is configured such that the source terminal is connected to the power supply potential and the drain terminal is connected to the first terminal. An operational amplifier differentially amplifies the voltage between a predetermined set voltage and the voltage at the first terminal so as to control the gate voltage of the P-channel type transistor.

Hall element control circuit

A focus control circuit is installed in an image pickup apparatus including a lens, a driver element for adjusting the position of the lens, and a position detecting element for detecting the position of the lens. A feedback equalizer included in the focus control circuit generates a drive signal used to adjust the position of the lens to a target position, based on a difference between the position of the lens identified by the output signal of the position detecting element and the target position of the lens set externally, and controls the driver element.

Focus control circuit for adjusting the focus by moving a lens

An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal. A control circuit connected to the refresh circuit produces the stop signal when it receives a sleep command and deactivates the stop signal when it receives a recovery command. Since the oscillator is stopped during the sleep mode, the disc player dissipates very little power in the sleep mode.

Optical disc player with sleep mode

A low-cost controller that operates in accordance with firmware stored in a memory. The controller includes a data processing circuit that performs predetermined processing on data and generates processed data. A write wire is connected to the memory, and a terminal is provided for use in the output of the data processed by the data processing circuit and/or the provision of the data to the data processing circuit. The controller includes a selector for connecting the write wire and the terminal to write the firmware to the memory.

Controller and data processing system

A CD-ROM decoder that performs code error correction and/or code error detection on digital data partitioned in sectors having a certain format includes a circuit for reading and analyzing the header information stored with each sector of CD-ROM data, which relieves a control microprocessor of having to perform such task. A header information register stores the header information for each sector of data. A sector information conversion circuit connected to the header information register determines the specific format of the sector data and generates corresponding sector information. The sector data and the corresponding sector information are stored in a buffer memory.

CD-ROM decoder and method for temporarily storing and retrieving digital data

A CD-ROM decoder for decreasing the load on a microcomputer. The CD-ROM decoder stores in a buffer memory in sector units digital data. The CD-ROM decoder includes a check head register for storing a first address of the buffer memory when storing the processed digital data in the buffer memory. A check sector counter counts the number of sectors of the processed digital data stored in the buffer memory to generate a count value. A command decision circuit decides whether digital data requested to be transferred is stored in the buffer memory based on the first address, the count value, and a head address of the digital data. The command decision circuit permits the CD-ROM decoder to transfer the processed digital data when deciding that the digital data requested to be transferred is stored in the buffer memory.

CD-ROM decoder

A code error correcting and detecting apparatus includes a controller that repetitively processes error correction and detection of encoded CD-ROM data, thereby relieving a control microprocessor of a CD-ROM system of the burden associated with such repetitive processing. The apparatus includes an error correction circuit that performs code error correction on digital data, such as digital data read from a CD, using an error-correcting code (ECC). An error detection circuit performs error detection on the error-corrected digital data using an error-detecting code (EDC) and determines whether there is an error. A control circuit causes the error-correction circuit to repeat its error-correction processing in accordance with the detection of an error by the error detection circuit.

Code error correcting and detecting apparatus

A small multichip module has a mother chip and a stack chip. The stack chip is stacked on the mother chip. The mother chip includes a first bonding pad located in a circuit area. A bonding pad of the stack chip is wire-bonded with the bonding pad of the mother chip.

Multichip module

A code error correcting apparatus, which can be used in a CD digital audio system, reads data stored on a disc, performs error correction, and transfers the error corrected data to another device, such as a computer, at an increased playback speed. The apparatus includes a digital processor which receives and processes (EFM demodulation) the data read from the disc, and a latch circuit connected to the processor for receiving the processed data. A memory is connected to the latch circuit by way of an input interface circuit, for storing the latched data. An error correction circuit connected to the memory reads the stored data, performs error correction on the data, and stores the error corrected data back in the memory. An output interface circuit is connected to the memory and provides an interface to the memory for external devices. The digital processor, the latch circuit, the input interface and the error correction circuit are all formed on a single substrate.

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Ichinomiya, Japan

Hiroyuki Tsuda