Honda Motor Co., Ltd.

Kabushiki Kaisha Toshiba

Hiroyuki Toshima

Natsuo Nakamura

Hisashi Kaneko

Nobuaki Miyakawa

Motoya Okazaki

Takahiro Kimura

A semiconductor integrated circuit device () which has a layered structure is composed of a plurality of semiconductor layers (L, L, L) in which an integrated circuit is formed on a substrate. Each of the semiconductor layers (L, L, L) has a semiconductor integrated circuit portion () that includes the abovementioned integrated circuit on a substrate (). Each of the semiconductor layers (L, L, L) also has on a substrate at least one unit of through-wiring () for electrically connecting the integrated circuit included in the semiconductor integrated circuit portion () to an integrated circuit of another semiconductor layer, and a surrounding insulation portion () for surrounding and insulating the through-wiring from the semiconductor integrated circuit portion. A structure formed by the surrounding insulation portion () and the through-wiring portion () composed of a plurality of units of through-wiring () reduces the resistance of the through-wiring portion and increases the degree of integration of a circuit.

Semiconductor integrated circuit device having insulated through wires

Adhesive injection apparatus, designed to inject an adhesive into gaps between a plurality of layers of flat plate members, includes: a receptacle for holding therein the flat plate members; an evacuation section for evacuating the interior of the receptacle and the gaps between the flat plate members; an adhesive supply section for supplying the adhesive into the receptacle; and a gas introduction section for introducing a gas into the receptacle to produce a pressure difference between the interior of the receptacle and the gaps between the flat plate members, so as to allow the adhesive to be injected from all around the flat plate members into the gaps.

Adhesive injection apparatus

According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.

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Saitama, Japan

Hiroyuki Toshima