Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Other

Hiroyuki Tanikawa

Toshihiro Tanaka

Yutaka Shinagawa

Masamichi Fujito

Takashi Yamaki

Yukiko Umemoto

Mitsuru Hiraki

Nozomu Matsuzaki

Yoshiaki Kamigaki

Shinichi Minami

Kozo Katayama

Kazufumi Suzukawa

Yoshiki Kawajiri

Norio Oza

Masayoshi Nakano

Koki Watanabe

A semiconductor device includes a plurality of nonvolatile memory cells (). Each of the nonvolatile memory cells comprises a MOS type first transistor section () used for information storage, and a MOS type second transistor section () which selects the first transistor section. The second transistor section has a bit line electrode () connected to a bit line, and a control gate electrode () connected to a control gate control line. The first transistor section has a source line electrode () connected to a source line, a memory gate electrode () connected to a memory gate control line, and a charge storage region () disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc&#x3c;tm.

Semiconductor device

A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.

Semiconductor integrated circuit

Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed

This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC among flash memory cells MC to MC formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL in which the memory cell MC is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL . As a result, parasitic capacitances Ca and Ca generated between p type wells PWL and PWL in which the unselected memory cells MC and MC are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.

Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system

A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

Nonvolatile memory and semiconductor device with controlled voltage booster circuit

In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three stages or more in a direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete the write or erase in a short time.

Non-volatile memory device with plurality of threshold voltage distributions

Growing community of inventors

Akishima, Japan

Hiroyuki Tanikawa