Sandisk Technologies Inc.

Hiroyuki Tanaka

Hiroyuki Ogawa

Raghuveer S Makala

Yanli Zhang

Ashish Kumar Baraskar

Naohiro Hosoda

Tadashi Nakamura

Sayako Nagamine

Ryo Nakamura

Akihisa Sai

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, and memory stack structures vertically extending through a respective one of the alternating stacks and located within the first memory array region and the second memory array region. An inter-array region containing lower and upper staircases is located between the first and the second memory array regions. The first memory array region may have a greater length than the second memory array region, or the lower staircase may generally ascend in an opposite direction from the upper staircase.

Three-dimensional memory device with off-center or reverse slope staircase regions and methods for forming the same

An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

Three-dimensional memory device containing direct contact drain-select-level semiconductor channel portions and methods of making the same

A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

3D NAND device with five-folded memory stack structure configuration

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.

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Yokkaichi, Japan

Hiroyuki Tanaka