Kabushiki Kaisha Toshiba

Nissan Motor Company Limited

Kioxia Corporation

Jatco Corporation

Toshiba Memory Corporation

Other

Yamaha Corporation

Hiroyuki Takenaka

Katsuhiko Hoya

Tadashi Miyakawa

Akihiko Chiba

Kenichiro Murakami

Tsuneo Inaba

Katsunori Satou

Kan Yagi

Hiroaki Nakasa

Osamu Sato

Hiroyuki Iwasaki

Sumio Tanaka

Hiroyuki Kanaya

Yoshinobu Kawamoto

Norihisa Arai

Tomio Katata

Yuzuru Tohta

Mitsuru Shimizu

Kiyofumi Sakurai

Takashi Nakazawa

Hiroshi Mochizuki

Osamu Hidaka

Kumi Okuwada

Teppei Higashitsuji

Mariko Iizuka

Youichi Magome

Jun Yoshino

Masaya Kubota

Sumito Ootsuki

Mitsushi Sonoda

Hiroshi Maejima

Takeshi Hamamoto

Hiroyuki Hara

Keisuke Nakatsuka

Go Endo

Nobuaki Okada

Shingo Nakazawa

Yoshiaki Takahashi

Takahiro Tsurudo

Masaki Unno

Hiroshi Takada

Yoshifumi Shimamura

Kenichi Matoba

Tsuyoshi Mori

Makoto Hashimoto

Tetsuo Enomoto

Mariko Ilzuka

Seiji Totsuka

Hitoshi Yokose

Seiji c/o Jatco Ltd Totsuka

Kan c/o Jatco Ltd Yagi

A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

Semiconductor memory device

A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Semiconductor storage device

A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.

According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.

Semiconductor storage device including variable resistance elements

A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.

A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Semiconductor memory device with efficient inclusion of control circuits

According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

Magnetoresistive memory device

A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

While a vehicle is decelerating starting at a braking start time, start-off pre-shifting starts when speed falls to a predetermined speed. At a vehicle stoppage time, an idle stop permission flag is not set to on if start-off pre-shifting is incomplete, even if idle stop permission conditions have been met. The idle stop permission flag is set to on when start-off pre-shifting is completed, and an idle stop flag is set to on and the engine stopped when engine rotational speed falls below a set speed. The engine is restarted in response to braking being released, and the idle stop flag is set to off and the idle stop control ended when the engine rotational speed reaches or exceeds a set speed. The restarting of the engine causes an engine-driven oil pump to dispense oil to be used as a medium to manifest an automatic clutch command hydraulic pressure.

Idle stop control device for vehicle equipped with automated manual transmission

A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.

Memory device

Under a specified condition where a torque converter is kept in a lockup state to prolong the fuel-cutoff time, because of vehicle coasting with an accelerator opening APO=0, a downshift command is generated and then an automatic transmission causes a reengagement downshift by a drop in a release-side clutch hydraulic pressure Poff and a rise in an engagement-side clutch hydraulic pressure Pon. During the reengagement downshift, the engagement-side clutch hydraulic pressure Pon is reduced from a high lockup-ON hydraulic pressure to a low lockup-OFF hydraulic pressure after the time when the lockup is predicted to be released, thus preventing a torque drawing-in tendency of transmission output torque, which may occur at the time of the beginning of the inertia phase, from increasing, and also reducing in the width of a subsequent change in vehicle deceleration G, and consequently enhancing the shift quality.

Coasting downshift control device for automatic transmission

According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

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Kamakura Kanagawa, Japan

Hiroyuki Takenaka