Kabushiki Kaisha Toshiba

Jfe Steel Corporation

Nec Electronics Corporation

Hiroyuki Takai

Mitsuhiro Okatsu

Yasumasa Takemura

Atsushi Kunimatsu

Masao Yuga

Toshiyuki Yaguchi

Seiji Koino

Tatsuo Koide

Hiroki Fujimura

Mikio Takasugi

Rikako Kato

A seamless steel pipe of the present invention is a seamless steel pipe having a composition that includes, in mass %, C: 0.02 to 0.12%, Si: 0.010 to 1.00%, Mn: 0.10 to 2.00%, P: 0.050% or less, S: 0.004% or less, Al: 0.010 to 0.100%, Cu: 0.03 to 0.80%, Ni: 0.02 to 0.50%, Cr: 0.55 to 1.00%, Sb: 0.005 to 0.20%, and the balance Fe and incidental impurities, and satisfying the following formula (1),1.7×Cu*+11×Cr*+3.8×Sb*≥13.5  (1),

Seamless steel pipe having desirable sulfuric acid dew-point corrosion resistance, and method for manufacturing same

A seamless steel pipe of the present invention is a seamless steel pipe having a composition including, in mass %, C: 0.01 to 0.12%, Si: 0.01 to 0.8%, Mn: 0.10 to 2.00%, P: 0.050% or less, S: 0.040% or less, Al: 0.010 to 0.100%, Cu: 0.03 to 0.80%, Ni: 0.01 to 0.50%, Mo: 0.01 to 0.20%, Sb: 0.002 to 0.50%, Cr: 0.004% or less, W: 0.002% or less, and the balance Fe and incidental impurities, and a structure including a ferrite phase having an area percentage of 50 to 65%, a pearlite phase having an area percentage of 2% or less, and one or both of a bainite phase and a martensitic phase representing the remainder, the seamless steel pipe having a yield strength of 230 MPa or more, and a tensile strength of 380 MPa or more.

A microcomputer is provided, which eliminates the need of input of a selection signal to select whether an external oscillator element is connected to generate an internal clock signal or an external clock signal is inputted to generate an internal clock signal. In this microcomputer, a delay circuit generates a delayed reset signal from an external reset signal to have a specific delay period. An external clock signal detection circuit detects an external clock signal at a second terminal, outputting a detection signal. An oscillation control signal generation circuit generates an oscillation control signal for an amplifier circuit, where the oscillation control signal is generated corresponding to a detection signal outputted from an external clock signal detection circuit. The oscillation control signal is used to activate the amplifier when the external clock signal does not exist at the second terminal and to inactivate the amplifier when the external clock signal exists at the second terminal. These operations are conducted in the specific delay period of the delayed reset signal.

Microcomputer operable with external and internal clock signals

An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

Processor architecture with divisional signal in instruction decode for

A microprocessor incorporating a cache memory with a selective purge operation includes a control register for storing control information including page information for controlling a purge operation for purging a predetermined page divided in the cache memory, a setting portion for transferring the control information to the control register; a comparator for comparing a target page address indicated by the control information stored in the control register with an address stored in the cache memory; and an issue portion for providing a purge command to indicate the start of execution of the purge operation to the comparator based on the control information stored in the control register only when the target page address agrees with an address in the cache memory.

Microprocessor incorporating cache memory with selective purge operation

A microprocessor consists of an arithmetic section for executing arithmetic processing with a program, a holding circuit for holding a designated address AD1 at which a piece of data DA1 is stored in an external memory, and a signal generating circuit for generating a signal when the designated address AD1 transmitted from the arithmetic section to the external memory is detected. The arithmetic section is provided with a cache memory for storing pieces of data, a tag memory for storing addresses at which the pieces of data are stored in the cache memory, a writing circuit for tagging the designated address AD1 stored in the tag memory after receiving the signal generated in the signal generating circuit, an arithmetic unit for executing arithmetic processing with the data stored in the cache memory, a brake signal generating circuit for generating a brake signal when the data DA1 stored at the designated address AD1 tagged is accessed by the arithmetic unit, and a control section for braking arithmetic processing executed in the arithmetic unit at a designated step of the program when the brake signal is provided from the circuit. The program used in the arithmetic unit is debugged after the arithmetic processing is braked.

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Tokyo, Japan

Hiroyuki Takai