Kabushiki Kaisha Toshiba

Hiroyuki Shibayama

Masayuki Koizumi

Shinsuke Fujii

Takuma Aoyama

According to an embodiment, a transmission circuit is configured to transmit a signal to a reception circuit through a transmitting AC coupling element. The reception circuit receives a signal through a receiving AC coupling element. The transmitting AC coupling element is AC coupled to the receiving AC coupling element. The transmission circuit includes a drive signal generation circuit and a drive circuit. The drive signal generation circuit is configured to generate a drive signal in synchronization with a transmission signal to be transmitted. The drive circuit is configured to cause, in response to the drive signal, a drive current to flow through the transmitting AC coupling element in synchronization with a rising edge and a falling edge of the transmission signal during a driving period set in advance.

Transmission circuit, reception circuit and communication system

According to an embodiment, a communication system includes a transmitting electrode, a first transmission line, a transmission circuit, a receiving electrode, a second transmission line and a reception circuit. The first transmission line includes one end connected to the transmitting electrode. The transmission circuit is connected to an other end of the first transmission line and configured to transmit a transmission signal. The receiving electrode is capacitively coupled to the transmitting electrode. The second transmission line includes one end connected to the receiving electrode. The reception circuit is connected to an other end of the second transmission line and configured to receive a reception signal via the receiving electrode and the second transmission line. Characteristic impedances of the first transmission line and the second transmission line are greater than an output impedance of the transmission circuit.

Communication system and transmitter

A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

Semiconductor device including current mirror circuit

An operational amplifieris provided with differential amplifier, replica amplifier, voltage-current converting circuit, reference current sourceand comparator. Differential amplifierincludes P-channel MOS transistors PTand PT, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT, NTand NT. Replica amplifieris identical in structure to differential amplifier and also includes P-channel MOS transistors PTand PT, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT, NTand NT. Voltage-current converting circuitconverts output voltages of replica amplifierto current Irep. Comparatorcompares output current Irep of voltage-current converting circuitwith reference current Iref of reference current sourceand supplies compared current Ico to differential amplifierto keep bias current Ibias of differential amplifierconstant.

Operational amplifier

A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line. If it is determined that the first bit line passes the current representing the data stored in the memory cell, the partial currents from the first bit line are recombined to provide an output and one of the partial currents from the second bit line is selected to provide another output. If it is determined that the first bit line does not pass the current representing the data stored in the memory cell, i.e., the first bit line passes the current representing the data stored in the dummy cell, the partial currents from the second bit line are recombined to provide an output and one of the partial currents from the first bit line is selected to provide another output.

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Kanagawa-ken, Japan

Hiroyuki Shibayama