Kabushiki Kaisha Toshiba

Samsung Electro-mechanics Co., Ltd.

Hiroyuki Sasaki

Hideo Kato

Hiroshi Watanabe

Seiichi Mori

Hidetoshi Saito

Kiyomi Naruke

Kazunori Kanebako

Takamichi Kasai

Hitoshi Araki

In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device

An electron beam deflection system is positioned outside of a main body of a color tube having a neck, inside of which electron beams extend horizontally, and a display unit extend laterally from the neck for displaying images by means of electron beams scanned from the electron beams. The system includes a pair of vertically opposed horizontal deflection coils, a pair of horizontally opposed vertical deflection coils, and a pair of vertically opposed coils outside the neck, each coil including a correction coil in a diametric direction of the neck for generating a magnetic field in an opposite direction to the direction or correcting a YV aberration. Therefore, the electron beam deflection system according to the invention has an effect of providing a color tube of high quality owing to its capability of correcting a variety of chromatic aberration in a wide range with a simple construction.

Beam deflection system and color tube

This invention discloses a memory cell threshold voltage shift method effective for the erase or write sequence of a nonvolatile semiconductor memory. First, the threshold voltages V of a plurality of memory cells are shifted at once to a range whose upper limit is set to an erase verify voltage V . After this, the lower limit of the threshold voltages V shifted at once to the range is shifted to a first overerase verify voltage V close to the erase verify voltage V . Then, the lower limit of the threshold voltages V shifted to the first overerase verify voltage V to a second overerase verify voltage V closer to the erase verify voltage V .

Nonvolatile semiconductor memory and threshold voltage control method therefor

A method of manufacturing a semiconductor memory device having a plurality of memory cells arranged in matrix includes forming a first masking layer on a semiconductor substrate of a first conductivity type and patterning the first masking layer to form a plurality of parallel strips which extend in first direction. A second masking layer is formed on the patterned first masking layer and the second masking layer is patterned to form a plurality of parallel strips which extend in a second direction perpendicular to the first direction. First impurities of a second conductivity type are implanted into the semiconductor substrate, using the patterned first and second masking layers as a mask, to form impurity regions of the second conductivity type. The patterned second masking layer is then removed and an insulating film is formed in the spaces between the parallel strips of the patterned first masking layer for isolating element regions on the semiconductor substrate. The insulating film covers the impurity regions of the second conductivity type. The patterned first masking layer is then removed and a conductive layer is patterned to form control gates for the memory cells in the element regions on the semiconductor substrate. Second impurities of the second conductivity type are implanted into the semiconductor substrate using the control gates as a mask to form self-aligned source regions for the memory cells, wherein the source region of a first memory cell is connected to the source region of a second memory cell by one of the impurity regions of the second conductivity type.

Method of manufacturing a semiconductor memory device including memory

A plurality of memory cells are formed on a semiconductor substrate. Each memory cell contains a first gate insulating film formed on the semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, a control gate formed on the second gate insulating film, and a source and a drain region formed in the semiconductor substrate on both sides of the floating gate, respectively. The source regions of the memory cells are connected with a plurality of common source lines. At least the surface of these source regions in the vicinity of the ends of the floating gate are made flush with the surface of the semiconductor substrate under the floating gate.

Method of manufacturing nonvolatile semiconductor memory device

A memory cell is formed in the main surface area of a semiconductor substrate. An inter-level insulation film is formed on the substrate to cover the memory cell. An opening is formed in the inter-level insulation film to reach the memory cell. An internal wiring layer is electrically connected to the memory cell via the opening. A protection film is formed on the inter-level insulation film to cover the internal wiring layer. The protection film is formed of a material containing at least silicon and oxygen and the refractive index thereof is set within a range of 1.48 to 1.65.

Growing community of inventors

Yokohama, Japan

Hiroyuki Sasaki