Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroyuki Sadakata

Naoki Kuroda

Ryuji Nishihara

Shoji Sakamoto

Masashi Agata

Masanori Shirahama

Kiyoto Ohta

Masahisa Iida

Kazunari Takahashi

Toshitaka Uchikoba

Koichiro Nomura

Yoshifumi Fukushima

A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.

Semiconductor integrated circuit

A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device.

Semiconductor memory device

A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines and a main bit line in an activated memory array to be connected all the time. With this configuration, it is possible to perform a disturb refresh test on a memory cell arrays basis regardless of the hierarchical bit line structure. Possibility of an erroneous read-out, which may be caused by connecting each of the hierarchical bit lines to one another and a consequent increase in a bit line load capacity, may be prevented by providing a timing control such that the switches are connected after a normal mode operation.

Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis

In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspondingly to each complementary sub bit line between the complementary sub bit line and a complementary main bit line corresponding to the complementary sub bit line. Furthermore, the semiconductor memory includes a hierarchical switch control unit for turning off all the sub bit line hierarchical switch and the complementary sub bit line hierarchical switch when a given signal is input.

Semiconductor memory and test method for the same

Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a refresh for memory cell arrays. This configuration needs no drastic addition of circuits and allows a reduction in disturb test time for a plurality of memory cell arrays.

Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

Semiconductor memory test device

In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMsandis set equal to that of the largest capacity RAMwithin the same chip, thereby making the X, Y address mapping the same for all the RAMsto

Semiconductor memory device and test method thereof

A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines. Thereby, it becomes unnecessary to separately provide strapping regions at the ends of memory cell array portions and it becomes unnecessary to increase the intervals between the memory cells by increasing the size of the memory cell in the layout according to the standard CMOS process and, therefore, contacts for strapping word lines can be provided for each memory cell, without increasing the area of memory cell array portions or the chip area, so that the propagation delay of drive signals in word lines can be reduced and high speed memory operation can be implemented.

A folded bitline type sense amplifier circuit is disposed at an outer side of an end memory cell array in which 2Tr1C type cells each composed of a data storage capacitor, an A port access transistor and a B port access transistor are arranged in the form of a matrix, and two word lines used for cell selection are connected to corresponding gates of the A and B port access transistors. The drain of the A port access transistor is connected to one bit line of an open bitline type sense amplifier circuit, and the drain of the B port access transistor is connected to one bit line out of a bit line pair of the folded bitline sense amplifier circuit.

Semiconductor memory

A semiconductor memory device includes memory array, first and second rows of sense amplifiers and selector. The memory array has first and second ports. The first and second rows of sense amplifiers are associated with the first and second ports, respectively. Responsive to a port selection signal, the selector selects the first or second port, through which burst data should be transferred, and couples the first or second row of sense amplifiers, associated with the port selected, to a data input or output circuit. If the selector has selected the first port, the device performs a refresh operation on the array using the second row of sense amplifiers while transferring the burst data through the first port. If the selector has selected the second port, the device performs the refresh operation on the array using the first row of sense amplifiers while transferring the burst data through the second port.

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Osaka, Japan

Hiroyuki Sadakata