Fujitsu Corporation

Fujitsu Quantum Devices Limited

Eudyna Devices Inc.

Hiroyuki Oguri

Teruo Yokoyama

Eizo Mitani

A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.

Semiconductor device and fabrication method of the same

A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.

Hetero-junction bipolar transistor with gold out-diffusion barrier made from InP or InGaP

A field effect transistor has a semiconductor lamination structure, a Schottky contact gate electrode and source/drain ohmic electrodes disposed on both sides of the gate electrode on the lamination structure, source/drain regions disposed under the source/drain electrodes, a channel layer disposed in the lamination structure spaced apart from the principal surface and connecting the source/drain regions, a barrier layer disposed in the lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than the channel layer, and a pair of impurity doped regions formed in the barrier layer and channel layer continuously with the source/drain regions on both sides of the gate electrode, wherein a carrier density in the barrier layer is lower than a carrier density in the channel layer in the impurity doped region. A filed effect transistor and its manufacture method are provided which can lower the source resistance of the field effect transistor while the gate breakdown voltage is maintained high.

Field effect transistor

An enhancement-mode semiconductor device includes a barrier layer formed on a channel layer and a gate electrode provided on the barrier layer, wherein the gate electrode is formed with an orientation chosen so as to maximize a threshold voltage of the semiconductor device.

Enhancement-mode semiconductor device

A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.

Growing community of inventors

Yamanashi, Japan

Hiroyuki Oguri