Sandisk Technologies Inc.

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Fujitsu Corporation

Advanced Micro Devices Corporation

Kabushiki Kaisha Toshiba

Toshiba Mitsubishi-electric Industrial Systems Corporation

Fujitsu Microelectronics Limited

Japan Aerospace Exploration Agency

Globalfoundries Inc.

Mitsubishi Heavy Industries Limited

Toshiba Elevator Kabushiki Kaisha

Hiroyuki Ogawa

Yasuhiro Sugita

Masato Hiramatsu

Shinji Yamagishi

Masayuki Jyumonji

Masakiyo Matsumura

Fumiaki Toyama

Kazutoshi Kida

Jixin Yu

James K Kai

Yu Nan Sun

Shinsuke Yada

Yuki Mizutani

Johann Alsmeier

Yukio Taniguchi

Kuo-Tung Chang

Hideyuki Kojima

Angela Tai Hui

Hiroyuki Kinoshita

Seiji Shimabukuro

Yoshinobu Kimura

Satoshi Shimizu

Shenqing Fang

Masatoshi Nishikawa

Yider Wu

Mitsuteru Mushiga

Daxin Mao

Taiji Ema

Tong Zhang

Toru Miwa

Masanori Tsutsumi

Naoki Takeguchi

Jean Mugiraneza

Jin Liu

Zhenyu Lu

Takenori Maruyama

Tomohiro Kimura

Hidehito Kitakado

Ritsuko Kawasaki

Akio Nishida

Kiyohiko Sakakibara

Kazuhide Tomiyasu

Jun Koyama

Minh Van Ngo

Yan Li

Masaaki Higashitani

Nian Niles Yang

Yanli Zhang

Hiroki Adachi

Zhigang Wang

Hiroyoshi Tomita

Ken Oowada

Hiroaki Maeda

Mikihiko Nishitani

Kohhei Tanaka

Akira Inoue

Zhixin Cui

Toru Anezaki

Seiichi Uchida

Murshed Chowdhury

Wenmei Li

Kazushi Fujita

Hardwell Chibvongodze

Shunpei Yamazaki

Yingda Dong

Raghuveer S Makala

Hidefumi Yoshida

Koichi Miyachi

Rahul Sharangpani

George Matamis

Tuan Duc Pham

Ching-Huang Lu

Richard M Fastow

Chi K Chang

Mitsuhiro Murata

Kenji Kasahara

Henry Chien

Yao-Sheng Lee

Kenichi Okada

Timothy J Thurgate

Seiji Kaneko

Unsoon Kim

Christopher James Brown

Hiromi Katoh

Satoshi Matsubara

Benjamin James Hadwen

Wei Zhao

Kaoru Yamamoto

Michiaki Sano

Yasuyuki Ogawa

Shigeyasu Mori

Hiroshi Matsukizono

Yoshikatsu Kuroda

Takashi Murai

Sateesh Koka

Yutaka Takamaru

Mikihiro Noma

Masayuki Hiroi

Katsuyoshi Matsuura

Fumitaka Amano

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures including a vertical channel and memory elements located in the memory openings, a contact via cavity vertically extending through the alternating stack, and an integrated contact-and-support assembly located in the contact via cavity. The integrated contact-and-support assembly includes a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity. A dielectric spacer is located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.

Three-dimensional memory device containing integrated contact-and-support assemblies and methods of making the same

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

High voltage field effect transistors with different sidewall spacer configurations and method of making the same

As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.

Sub-block separation in NAND memory through word line based selectors

A bonded assembly includes a first memory die and a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory opening fill structures, a first stepped dielectric material portion, and first column-shaped conductive via structures including a respective conductive shaft portion vertically extending through a respective subset of the first electrically conductive layers, a respective conductive base portion, and a respective conductive capital portion contacting a horizontal surface of a respective one of the first electrically conductive layers. The logic die includes logic-side bonding pads that are bonded to the first column-shaped conductive via structures.

Bonded assembly containing conductive via structures extending through word lines in a staircase region and methods for making the same

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.

Field effect transistors with reduced gate fringe area and method of making the same

A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, forming memory openings formed in the memory array region and monitor openings formed in a monitor region though the alternating stack, forming memory opening fill structures in the memory openings, forming monitor opening fill structures by depositing a monitor opening fill material in the monitor openings, recessing first portions of the alternating stack in a contact region and second portions of the alternating stack in the monitor region, and determining at least one characteristic of the recessed surfaces of the monitor opening fill structures. At least one characteristic of the memory openings or memory opening fill structures may be determined based on the determining at least one characteristic of the recessed surfaces of the monitor opening fill structures.

Three-dimensional memory device containing memory opening monitoring area and methods of making the same

A memory system having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its NAND strings connected to a different set of contiguous bit lines. In an aspect the memory operation is a program operation with selected memory cells in each of the multiple XY sub-blocks programmed in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the block. In one aspect, the memory operation is an erase operation.

X-direction divided sub-block mode in NAND

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Three-dimensional memory device with separated contact regions

A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

Semiconductor wafer configured for single touch-down testing

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Transistor circuits including fringeless transistors and method of making the same

A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.

Three-dimensional memory device with separated contact regions and methods for forming the same

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, and memory stack structures vertically extending through a respective one of the alternating stacks and located within the first memory array region and the second memory array region. An inter-array region containing lower and upper staircases is located between the first and the second memory array regions. The first memory array region may have a greater length than the second memory array region, or the lower staircase may generally ascend in an opposite direction from the upper staircase.

Three-dimensional memory device with off-center or reverse slope staircase regions and methods for forming the same

A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Three-dimensional memory device including sense amplifiers having a common width and separation

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Hiroyuki Ogawa