Kabushiki Kaisha Toshiba

Hiroyuki Noji

Tohru Furuyama

Donald C Stark

Yusuke Kohyama

Shigeo Ohshima

Satoru Takase

Koichi Fukuda

Natsuki Kushiyama

Tomoki Higashi

Kiyofumi Sakurai

Koichi Kishi

Soichi Sugiura

A semiconductor integrated circuit device, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

Semiconductor integrated circuit device and method for monitoring its internal signal

A first bonding pad is formed on the surface of a semiconductor chip on which a semiconductor circuit is formed. A first insulating substrate is formed on the semiconductor chip, and a wiring layer is formed on the first insulating substrate. A second insulating substrate is formed on the first insulating substrate and wiring layer. A first region is formed by forming an opening in the second insulating substrate to expose part of the surface of the wiring layer. The first region and first bonding pad are connected by a wire. A second region is formed by forming an opening in the second insulating substrate to expose part of the surface of the wiring layer. In the second region, a bump is formed. Further, a third region is formed by forming an opening in the second insulating substrate to expose part of the surface of the wiring layer. The third region has at least an area necessary for the terminal of a measurement device to contact the third region in operation measurement.

Semiconductor device having external connection terminals formed in two-dimensional area

A semiconductor integrated circuit device is disclosed, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

Semiconductor integrated circuit device and method for monitoring its

The present invention intends to provide a semiconductor device integrated circuit having an additive circuit capable of the evaluation of the dynamic performance of a memory block in a mixed logic and memory IC or a high-speed logic block in a semiconductor device integrated circuit, directly from the outside of the device. In order to evaluate the dynamic performance of the memory block or the high-speed logic block by using a tester, the device is provided on the chip with bus lines which bypass the peripheral logic and are connected to the input terminals of the memory block or the high-speed logic block. In the device, the delay time difference between the bus lines are measured from the outside of the device, at first. By use of the measurement result, the timing error of inputting a plurality of test pulse signals used for the dynamic performance evaluation is compensated. A switching element is provided between the reference line and each of the bus lines. A delay time measuring signal is input to each of external I/O pads connected to the bus line through which the delay time of the signal passing is measured, and then the differences in the delay time of all the bus lines are obtained on the basis of the signal delay time produced between the reference line and the each of the line. By use of the difference in the delay time of the lines, the input timing error when the memory block is measured with the tester is compensated, thereby precise evaluation of the memory block or the high-speed logic block is obtained.

Semiconductor integrated circuit

A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

Semiconductor memory device

According to this present invention, a semiconductor device includes source and drain diffusion layers, and a gate electrode formed on a substrate between the source diffusion layer and the drain diffusion layer. In addition, antioxidant films are respectively formed on the source diffusion layer and the drain diffusion layer. These antioxidant films are used for controlling a diffusion rate of an impurity contained in the source diffusion layer and the drain diffusion layer.

Semiconductor device having film for controlling diffusion of impurity

There is provided a semiconductor memory including a plurality of word lines, a plurality of bit lines intersecting the word lines, and a memory cell array having memory cells arranged at respective intersections of the word lines and bit lines. Word line selecting circuits select the word lines in accordance with an address signal and word line driving circuits are connected to the word lines for driving selected word lines. Selective stress applying circuitry selectively applies stress, during a stress test, to word lines in one of a plurality of word line groups into which all word lines are classified. The selective stress applying circuits includes an arrangement of MOS transistors and pads for applying stress to a word line group during the stress test.

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Chigasaki, Japan

Hiroyuki Noji