Texas Instruments Corporation

Seiko Epson Corporation

Tetra Laval Holdings & Finance S.a.

Inoac Corporation

Hiroyuki Nishimura

Toshiaki Yoshino

Satoshi Shinada

Hisashi Koike

Michinari Tsukahara

Tomio Yokoyama

Yuzo Otsuka

Shigehiro Kinoshita

Takeo Yamazaki

Ikuyoshi Ochiai

Shinsuke Yamada

Toshichika Matsunaga

Disclosed is a resinous filter for an ink-jet recording apparatus, which is obtained by a process comprising: adding common salt to a melt of a resin comprising at least one member selected from the group consisting of polyethylenes having a number-average molecular weight of from 30,000 to 80,000 and polypropylenes having a number-average molecular weight of from 50,000 to 100,000; kneading the resultant mixture to prepare a melt to be molded; molding the melt to be molded to obtain a molding; and washing the molding with water to remove the salt therefrom.

Resinous filter for ink-jet recording apparatus

The present invention provides a filling apparatus establishing positional coincidence between creases preformed in a packaging material and actual creases to thereby improve the appearance of a packaging container. A light source irradiates a portion of the outer circumferential surface of a packaging material tube which includes an overlap. A sensor receives light emitted from the light source and reflected from the outer circumferential surface of the tube. The overlap is detected as a peak in the sensor output. Light reflected from an edge portion of the packaging material exhibits greater intensity and is seen as a peak in the sensor output indicating position of the overlap.

Filling machine

An improved flip-flop is disclosed. The flip-flop (12) includes a latch circuit (22) that receives an input signal and a clock signal. The latch circuit (22) generates an output signal that tracks the input signal during a first portion of the clock signal, and remains constant during a second portion of the clock signal. A master flip-flop (36) receives the clock signal and the output signal of the latch circuit, and generates an output signal that tracks the output signal of the latch circuit (22) during the second portion of the clock signal, and remains constant during the first portion of the clock signal. A slave flip-flop (48) receives the clock signal and the output signal of the master flip-flop and generates an output signal. The output signal tracks the output signal of the master flip-flop (36) during the first portion of the clock signal and remains constant during the second portion of the clock signal. The flip-flop may be incorporated into a shift register (10). The flip-flop provides automatic compensation for line delays in the clock signal without the need for custom-designed delays built into the clock signal lines.

Flip-flop

An nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present and which allows high-speed computing operations. The nth degree function computing device comprises two series operators 32 and 38 connected in series, with an adder 44 inserted between them, and with an adder 48 inserted between the output terminal of the second-stage series operator 38 and device output terminal 46. A constant 2a.sub.2 is sent from constant generator 50 to the first input terminal of an adder 34 of the first-stage series operator 32. A constant (a.sub.1 -a.sub.2) is sent from constant generator 52 to first input terminal of adder 44. A constant a.sub.0 is sent from constant generator 54 to the first input terminal of adder 48. With respect to variable x (integer), a clock circuit 56 sends (x+1) synchronized clock pulses CLK.sub.i and x clock pulses CLK.sub.k to registers 36 and 42 of first-stage and second-stage series operators 32 and 38, respectively.

Computing device for nth degree functions

A digital filter, in which the operation time can be kept short even when the order of the filter is high. The digital filter comprises a first transversal filter TF.sub.1 which has an input terminal connected to a signal input terminal 10, first delay means DR.sub.1 which has an input terminal connected to the output terminal of first transversal filter TF.sub.1, a second transversal filter TF.sub.2 connected to the output terminal of the first delay means DR.sub.1, second delay means DR.sub.2 which has an input terminal connected to the output terminal of the second transversal filter TF.sub.2, adder AD which has one of the input terminals connected to the output terminal of the second delay means DR.sub.2, third delay means DR.sub.3 which has an input terminal connected to the output terminal of the adder AD and an output terminal connected to the signal output terminal, and a third transversal filter TF.sub.3 which has an input terminal connected to the output terminal of the aforementioned third delay means DR.sub.3 and an output terminal connected to the other input terminal of the aforementioned adder. In this digital filter, the chain configuration of the operator that determines the time needed for one cycle of operation is a multiplier-adder chain including one multiplier and one adder in each transversal filter. Consequently, its operation time is equal to the sum of the operation times needed by one multiplier and one adder and is unrelated to the order of each transversal filter, that is, the order of the digital filter.

Infinite impulse response digital filter with plural processing units

Growing community of inventors

Kanagawa, Japan

Hiroyuki Nishimura