Kabushiki Kaisha Toshiba

Hiroyuki Moro

Toshihiko Kaneshige

Yukiyasu Tatsuzawa

Hideyuki Yamakawa

Koichi Otake

Tohru Fukuda

Takahiro Nango

Motohiro Matsuyama

Akinori Harasawa

Takami Sugita

Takayoshi Fushinuki

According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Memory control device, storage device, and memory control method

According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the respective channels. The controller is configured to write calibration data to the nonvolatile memories of any channel designated, through the interface module at the same time, in order to perform calibration.

Data storage apparatus and method of calibrating memory

According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected.

Data storage device and method for checking and correcting errors

According to one embodiment, a semiconductor memory device includes a command processing module, a plurality of storage units, a plurality of control modules, an adjustment circuit, and a setting register. The adjustment circuit is configured to exclude the control module connected to the storage unit of a second group from a write operation in accordance with identification data, and to cause the control module connected to the storage unit of the second group to perform a read operation in a period overlapping the write operation performed by the control module connected to the storage unit of a first group.

Semiconductor memory device and method of reading data from and writing data into a plurality of storage units

According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Data storage apparatus and method for writing data

According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

Semiconductor storage device and method of controlling semiconductor storage device

A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.

Memory card authentication system, capacity switching-type memory card host device, capacity switching-type memory card, storage capacity setting method, and storage capacity setting program

A system for authenticating a memory card including a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card, a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device, and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.

A disk device includes a reading section which reads reflected light and outputs a read signal according to the read reflected light, a processing section which calculates an adjustment value from the read signal, performs predetermined processing on the read signal based on the adjustment value, and outputs a process signal, a detecting section which detects a reading defect in the reading section based on the read signal, a determining section which determines signal quality of the process signal output from the processing section, a storage section which stores the adjustment value calculated by the processing section, in a memory area, based on a result output from the determining section, and a controller which, when the detecting section detects the reading defect, performs control so that the adjustment value is read out of the storage section and is supplied to the processing section.

Disk device and disk reproduction method that prevents a wrong reproducing operation when a defect on the disk is determined

A recorded stream generator generates a data block stream in synchronism with the phase of a recording clock, from the input data. The recorded stream generator further generates, for each predetermined data unit constituting the data block stream, a data phase reference pulse indicative of the phase of the data unit. An inserting section inserts a VFO signal into a predetermined amount (32 sectors) of the data block stream, the VFO signal having a length of time corresponding to a difference in phase between an wobble address phase signal and a data phase reference pulse. The inserting section thus provides a data stream DST consisting of the VFO signals and the data block streams. An LD uses light beams to record the data stream on an optical disk.

Optical disk apparatus, method of recording information, and information recording medium

A disk apparatus has an equalizing unit which performs PR equalization for the read signal from the disk based on a plurality of tap coefficients, a decoding unit which performs a decoding process for the equalized read signal, a calculating unit which obtains an ideal signal of the decoded read signal, and compares the ideal signal with the decoded read signal, thereby calculating an error signal E, and a control unit which groups the tap coefficients into at least a first and second coefficient groups which are groups of tap coefficients at symmetrical locations each, and determines tap coefficients of the first coefficient group in a range of a first limit value Kaccording to the calculated error signal, determines tap coefficients of the second coefficient group in a range of a second limit value and supplies the determined tap coefficients to the equalizing unit.

Disk apparatus and method using plural tap coefficient equalization

A disk apparatus has a reading unit which reads reflection light from a disk and outputting a read signal, an identifying unit which identifies whether the read signal has been modified in accordance with a first modulation rule or has been modulated in accordance with a second modulation rule and outputs an identification signal, an equalizing unit which applies a waveform equalizing process to the read signal, and a decoding unit which carries out likelihood decoding of the waveform equalized read signal according to the modulation rule indicated by the identification signal from the identifying unit, and outputs a reproduction signal.

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Ome, Japan

Hiroyuki Moro