International Business Machines Corporation

Omron Corporation

Hiroyuki Mori

Keishi Okamoto

Toyohiro Aoki

Akihiro Horibe

Yasumitsu K Orii

Takahito Watanabe

Kazushige Toriyama

Takashi Hisada

Eiji Nakamura

Risa Miyazawa

Keiji Matsumoto

Katsuki Nakajima

Hirokazu Noma

Mayuko Tanaka

Kamal Kumar Sikka

Kuniaki Sueoka

Ting-Li Yang

Sayuri Hada

Kimihiro Yamanaka

Takako Onishi

Kazushige Kawasaki

Isao Nakanishi

Paul Stephen Andry

Marc Adam Bergendahl

Vijayeshwar Das Khanna

Patrick Ruch

Yang Liu

Yutaka Tsukada

Ravi K Bonam

Dale Curtis McHerron

Isabel De Sousa

Maryse Cournoyer

Pascale Gagnon

Catherine Dufort

Kazuto Kojitani

Charles C Bureau

Yoshihiro Nagao

Naohiro Kawai

Kaoru Kobayashi

Mayuko Kishimoto

Shintaro Yamamichi

Mitsuya Ishida

Keiji Otaka

Yoshiaki Hiraoka

Hisashi Sugihara

Yoshiyuki Yamaji

Akira Matsushita

Dishit Paresh Parekh

Keita Saji

Shimpei Fujii

Akihiro Kawata

Yoshiharu Ogura

Masaomi Yoshida

A management system for a manufacturing facility including a manufacturing device including one or more device members for manufacturing a product, and an inspection device, the system including a display unit, a device member information acquisition unit, a product member information acquisition unit, a manufacturing abnormality information acquisition unit, an improvement candidate information acquisition unit configured to acquire improvement candidate information about candidates for improvement in the manufacturing facility, and a management work support unit configured to create list information and to cause the display unit to display the list information, the list information including an aggregated value of abnormalities of each sort during manufacturing the product and an aggregated value of abnormalities of each sort during inspecting the product within a predetermined aggregation time period, for each device member and/or product member as the candidate for improvement.

Management system, management device, management method, and program

Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.

Layer-to-layer registration measurement mark

Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.

Bonding of bridge to multiple semiconductor chips

An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

Controlling of height of high-density interconnection structure on substrate

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Direct bonded heterogeneous integration silicon bridge

Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.

Side pad anchored by next adjacent via

Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.

Restoring a wearable biological sensor

Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.

Fabricating an interconnection using a sacrificial layer

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.

Prevention of bridging between solder joints

An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.

Interconnection with side connection to substrate

An inspection management system having a plurality of processes and managing final inspection performed to inspect a completed product and one or more intermediate inspections performed to inspect an intermediate product manufactured in the processes earlier than a final process includes: an inspection content data acquisition unit that acquires inspection content data including an inspection standard for each inspection item of the product; an inspection content setting unit that sets inspection content based on the inspection content data acquired by the inspection content data acquisition unit; a simulation unit that simulates inspection in accordance with assumed inspection content; an inspection standard calculation unit that calculates an inspection standard more appropriate than a current inspection standard based on the simulation; and an output unit that outputs base information indicating that at least the inspection standard calculated by the inspection standard calculation unit is more appropriate than the current inspection standard.

Inspection management system, inspection management apparatuses, and inspection management method

The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.

Laminated circuitry cooling for inter-chip bridges

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

Growing community of inventors

Yasu, Japan

Hiroyuki Mori