Sony Corporation

Siemens Aktiengesellschaft

Hiroyuki Miwa

Takayuki Gomi

Katsuyuki Kato

Hiroaki Ammo

Hiroaki Anmo

Takashi Noguchi

Hirokazu Ejiri

Shigeru Kanematsu

Norikazu Ouchi

Minoru Nakamura

Tomotaka Fujisawa

Akio Kayanuma

Mamoru Shinohara

Koji Kobayashi

Chihiro Arai

Hiroki Hozumi

Norikazu Ohuchi

Norikazu Chuchi

A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening disposed in the first conductive film. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer in the third impurity diffusion layer is formed in the opening surrounded by the side walls.

Method of making a bipolar transistor having a reduced base transit time

A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.

Semiconductor device and manufacturing method of the same

A method of production of a semiconductor device able to be miniaturized by preventing the decline of the h at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode. Further, the external base region connected to the intrinsic base region is formed on the semiconductor substrate surface by self-alignment with respect to the emitter electrode.

Method of production of semiconductor device

Disclosed is a method of fabricating a semiconductor device in which at least an LDD type insulated-gate field effect transistor and a bipolar transistor are formed on a common base substrate. An insulating layer for forming side walls of an LDD type insulated-gate field effect transistor is formed by a stack of first and second insulating films. An opening is formed in the lower first insulating film at a position in a bipolar transistor forming area, and a single crystal semiconductor layer is formed on a base substrate through the opening. With this configuration, the fabrication steps can be simplified and the reliability of the semiconductor device can be enhanced.

Method of fabricating semiconductor device

A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor whereas the other doped polysilicon film is used for emitter of the NPN and a base of the PNP. The resulting base and emitter isolating structure is easy to fabricate, and self-aligned to the advantage of size reduction of individual devices.

Structure and fabrication of bipolar transistor

A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of forming a gate electrode (the first semiconductor layer) on a substrate; forming an insulating film; forming a second semiconductor layer; leaving the second semiconductor layer and the insulating film on the bipolar part and removing them on the CMOS part to form sidewalls on the side faces of the gate electrode; forming source/drain regions; forming a Ti layer over the entire surface and forming silicide on the surfaces of the second semiconductor layer, the source/drain regions, and the gate electrode; and forming a base electrode by patterning the second semiconductor layer.

Method of producing semiconductor device

A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.

Method of manufacturing semiconductor resistors

A p+ type graft base layer is formed both in a base layer of a p type epitaxial layer in a base opening of an insulating layer formed on a collector layer of an n type epitaxial layer and on an upper layer of the n type epitaxial layer contacting the p type epitaxial layer so that the graft base layer is positioned near the edge of the base opening, whereby a pn junction is formed away from the edge of the base opening where crystallinity of the p type epitaxial layer is deteriorated.

Bipolar transistor and its manufacturing method

In order to prevent an epitaxial layer from contamination by metal when the epitaxial layer is formed on a substrate on which a conductor film comprising a metallic film is formed, a bipolar transistor (semiconductor device) 1 has the first conductor pattern 8 comprising a high-melting metallic film or a high-melting metallic compound film formed on the substrate 4, and the second conductor pattern 9 comprising a non-metallic film formed so as to cover the first conductor pattern 8. On the substrate 4 is formed the first conductivity type base layer 10 on the semiconductor layer comprising an epitaxial layer so as to come in contact with the second conductor pattern 9. Furthermore, when manufacturing the bipolar transistor 1, the semiconductor layer as the base layer 10 is formed with the epitaxial process after the first conductor pattern 8 is covered by the second conductor pattern 9.

Semiconductor device and method of manufacturing the semiconductor device

A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Semiconductor device and its manufacturing method

Structure of complementary bipolar transistors

A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Manufacturing method for making bipolar device having double polysilicon

A bipolar transistor has a performance and high reliability, which are by enhancing a withstand voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, a first conductive film connected to the first diffusion layer, and an opening disposed in the first conductive film. A second impurity diffusion layer is formed in a portion, exposed from the opening portion, of the semiconducting substrate and is connected to the first impurity diffusion layer. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer is formed in the third impurity diffusion layer in the opening surrounded by the side walls.

Method for forming bipolar transistor having a reduced base transit time

A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

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Kanagawa, Japan

Hiroyuki Miwa