Sharp Kabushiki Kaisha Corporation

Hiroyuki Matsuoka

Kengo Sudoh

Hidenori Minoda

Hiroshi Ii

Katsuaki Matsufuji

Clocks of various types of input digital audio signals having different sampling frequencies, for example 48.1 KHz, 44.1 KHz and 32 KHz, are extracted by a PLL circuit. The input digital audio signals are converted into signals of a predetermined sampling frequency, for example 41.1 KHz, on average based on the extracted clocks by a frequency converter circuit, and then converted into signals of a uniform output rate by an FIFO circuit. The signals of a uniform output rate from the FIFO circuit are converted into analog outputs by a D/A converter. In this structure, when reproducing the input digital audio signals as monitor sounds while recording the input digital audio signals, it is possible to achieve an improvement of the monitor sounds.

Digital audio device

A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

Digital PLL circuit

A digital phase-locked loop system having an oscillator which generates a clock signal of a stationary frequency, a frequency divider which frequency-divides the clock signal to produce a phase-locked loop clock signal, a phase difference detector which detects a phase difference between an input signal and the phase-locked loop clock signal and outputs a phase difference detection signal, and a frequency dividing rate setting device to set a frequency dividing rate corresponding to the phase difference in response to the phase difference detection signal and apply the rate to the frequency divider. The phase difference detector includes a first counter to detect a phase difference at a leading edge of the clock signal from the oscillator and a second counter to detect it at a trailing edge of the clock signal. The frequency dividing rate setting device includes an adder to add the phase differences detected by the first and second counters, a latch to hold an addition result produced by the adder, and a decoder to decode the frequency dividing rate corresponding to the addition result held by the latch. The frequency divider frequency-divides the clock signal according to the frequency dividing rate decoded by the decoder and newly generates a phase-locked loop clock signal.

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Higashihiroshima, Japan

Hiroyuki Matsuoka