Sumitomo Electric Industries, Limited

Denso Corporation

Other

Japan Science and Technology Agency

Kyocera Corporation

National Institute for Materials Science

Hiroyuki Matsunami

Tsunenobu Kimoto

Shin Harada

Kenichi Hirotsu

Kazuhiro Fujikawa

Satoshi Hatsukawa

Takashi Hoshino

Yuuichi Takeuchi

Jun Suda

Hiromu Shiomi

Mitsuhiro Kataoka

Masami Naito

Rajesh Kumar

Hiroyuki Kinoshita

Rajesh Kumar Malhan

Satoshi Kamiyama

Hiroshi Amano

Isamu Akasaki

Shigeki Otani

Norio Onojima

Shin c/o Osaka Works Of Sumitomo Electric Harada

Kenichi c/o Osaka Works Of Sumitomo Hirotsu

Tsunenobu 1-39-605 Matsudairachikuzen Kimoto

Shin c/o Osaka Works Harada

Kazuhiro c/o Osaka Works Fujikawa

Shin Osaka Works Sumitomo Elec Ind Ltd Harada

Kenichi Osaka Works Sumitomo Elec Ind Hirotsu

A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is &#x3c;11-20&#x3e;. A trench is formed on the SiC to have a stripe structure extending toward a &#x3c;11-20&#x3e; direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Silicon carbide semiconductor device

A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Lateral junction field effect transistor and method of manufacturing the same

SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrateis rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrateis then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrateis etched so as to form a clean SiC surfaceon the substrate surface. The SiC substrateis then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10to 10Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beamat time tat temperature of 800&#xb0; C. or lower and performing a heating treatment at 800&#xb0; C. or higher is repeated at least once. The temperature is then set to the growth temperature of an AlN film, and the SiC substrate surfaceis initially irradiated with Al atomsin ultrahigh vacuum state, followed by the feeding of N atoms

Method of growing semiconductor crystal

A field effect transistor comprises a SiC substrate, a sourceand a drainformed on the surface of the SiC substrate, an insulating structure comprising an AlN layerformed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiOlayer formed thereon, and a gate electrodeformed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

Field effect transistor and method for manufacturing same

A lateral JFET has a basic structure including an n-type semiconductor layer () formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (). Moreover, in the p-type semiconductor layer, there are provided a p-type gate region layer () extending into the n-type semiconductor layer () and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer () and an n-type drain region layer () spaced from the p-type gate region layer () by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Lateral junction field-effect transistor

On an SiC single crystal substrate, an electric field relaxation layer and a p&#x2212; type buffer layer are formed. The electric field relaxation layer is formed between the p&#x2212; type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p&#x2212; type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

Field effect transistor

Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrateof diboride XB(where X is either Zr or Ti) which is facially oriented in a (0001) planeand has a thickness of 0.1 mm or less. The substrateis permitted cleaving and splitting along a (10-10) planewith ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Diboride single crystal substrate, semiconductor device using this and its manufacturing method

A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600&#xb0; C.

Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate

A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region () of a second conductivity type provided on a surface of a semiconductor substrate, a source region () of a first conductivity type, a channel region () of the first conductivity type that adjoins the source region, a confining region () of the second conductivity type that adjoins the gate region and confines the channel region, a drain region () of the first conductivity type provided on a reverse face, and a drift region () of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.

Pinch-off type vertical junction field effect transistor and method of manufacturing the same

A SiC wafer comprises a 4H polytype SiC substrate in which the crystal plane orientation is substantially &lcub;03-38&rcub;, and a buffer layer composed of SiC formed over this SiC substrate . The &lcub;03-38&rcub; plane forms an angle of approximately 35&deg; with respect to the <0001> axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer on the buffer layer . Lattice mismatching between the SiC substrate and the active layer is suppressed by the buffer layer . Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

SiC wafer, SiC semiconductor device, and production method of SiC wafer

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Yawata, Japan

Hiroyuki Matsunami