Hitachi, Ltd.

Hiroyuki Kurosawa

Yasuo Inoue

Hidefumi Masuzaki

Hidehiko Iwasaki

Naoya Takahashi

Soichi Isono

Masayuki Hoshino

Tatuya Ninomiya

Mitsuru Inoue

Kiyoshi Hisano

Shuji Sugimoto

Ken Hirashima

Kenji Kubota

A storage system, coupled to a host computer, including at least one controller receiving data from the host computer, and a plurality of memory units connected to the controller. The controller generates parity data and sends the data and the parity data to the memory units. The memory units include a semiconductor memory device which stores the data and the parity data permanently.

Storage system having a semiconductor memory device which stores data and parity data permanently

A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.

Storage system having data format conversion function

Storage system

A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation. Since plurality of first logical units, the plurality of second logical units, and the plurality of cache memories allow hot replace, the storage system can realize its non-stop maintenance.

Storage system having plural buses

The host adaptor packages,and the disk adaptor packages,which constitute the magnetic disk subsystem,are connected to the common bus,consisting of a data bus, a control bus, and a power line in the hot replacement ready state. The packages,and,have the control means,and the clock generator,and when a failure occurs in respective packages, the package replace controller,mounted in the control means,executes the blocking processing for the bus driver,and the clock generator,If this occurs, the clock generator,enters the stopped state, so that the circuit in the package enters the reset state and the package function is stopped, that is, the package enters the blocked state. As a result, hot replacement of the closed package can be executed without affecting the operation of the system.

Package blocking method for a storage system having a bus common to a plurality of kinds of groups of packages

Storage system realizing scalability and fault tolerance

The host adaptor packages 4 and the disk adaptor packages 6 which constitute the magnetic disk subsystem 1 are connected to the common bus 3 consisting of a data bus, a control bus, and a power line in the hot replacement ready state. The packages 4 and 6 have the control means 11 and the clock generator 14 and when a failure occurs in respective packages, the package replace controller 13 mounted in the control means 11 executes the blocking processing for the bus driver 15 and the clock generator 14. If this occurs, the clock generator 14 enters the stopped state, so that the circuit in the package enters the reset state and the package function is stopped, that is, the package enters the blocked state. As a result, hot replacement of the closed package can be executed without affecting the operation of the system.

Package blocking method for a storage system having a bus common to a

Storage system having a bus common to a plurality of kinds of groups of

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

External memory control techniques with multiprocessors improving the

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

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Hiratsuka, Japan

Hiroyuki Kurosawa