Renesas Electronics Corporation

Nec Electronics Corporation

Hiroyuki Kunishima

Toshiyuki Takewaki

Yasutaka Nakashiba

Tatsuya Usami

Keiji Sakamoto

Shinichi Watanuki

Yoshiaki Yamamoto

Ken Ozawa

Nobuo Hironaga

Norio Okada

Hidemitsu Aoki

Noriaki Oda

Naoya Inoue

Daisuke Oshida

Manabu Iguchi

Hiroaki Tomimori

Kenichiro Hijioka

Masaru Wakabayashi

Ippei Kume

Masashige Moritoki

Youichi Yamamoto

Hiroki Shirai

Toshiji Taiji

Kazutoshi Shiba

Kenichi Nakabeppu

A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

Semiconductor device

Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.

Optical semiconductor device, and method for producing the same

A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.

Semiconductor device and manufacturing method of the same

A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.

Optical semiconductor device

Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).

Semiconductor device and method of manufacturing the same

A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [&#x3bc;m], the following expression (1) is satisfied.&#x2266;1.98 [nF/&#x3bc;m]&#x2003;&#x2003;(1) The elution of the second electrode constituting the capacitor at the lower ends of the coupling holes is suppressed.

To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

Semiconductor device with protective layer and method of manufacturing same

A semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.

Semiconductor device having interconnect structure for MIM capacitor and fuse elements

Provided is a reticle used for forming a plurality of vias for connecting first wirings provided in a first wiring layer and second wirings provided in a second wiring layer formed above the first wiring layer. The first wirings and the second wirings are provided along one of a first direction and a second direction, and the first direction and the second direction perpendicularly cross each other. The reticle includes a plurality of via opening patterns for forming the plurality of vias. Each of the plurality of via opening patterns has a rectangular shape, and is arranged to cause each side of each of the via opening patterns to be diagonal with respect to the first direction and the second direction.

Reticle, and method of laying out wirings and vias

In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.

Semiconductor device featuring large reinforcing elements in pad area

A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the insulating film. The copper interconnection includes: a first copper interconnection having a relatively narrow width; and a second copper interconnection having a relatively wide width. The first copper interconnection has the top surface thereof principally composed of copper, and the second copper interconnection has the top surface thereof principally composed of copper.

Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces

An interconnect trench is formed on a dielectric layerand a first HSQ layerformed on a semiconductor substrate, and a tantalum family barrier metal layeris formed all over the substrate. Then a seed copper-containing metal layerand a plated copper layerare formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layeris formed on the plated copper layerso as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layerdiffuses uniformly into the plated copper layer

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a first wiring line composed of a copper containing metal film is formed on or above a semiconductor substrate. A first interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the first wiring line. The first interlayer insulating film is selectively removed to form a connection hole reaching the first wiring line. A barrier metal film is formed to cover an inner surface of the connection hole and then a copper containing metal film is formed to fill the connection hole. The copper containing metal film formed outside the connection hole is removed. A second interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the copper containing metal film formed in the connection hole. The second interlayer insulating film is selectively removed to form a wiring line groove such that the copper containing metal film formed in the connection hole is exposed at a bottom. A barrier metal film is formed to cover an inside of the wiring line groove and then a copper containing metal film is formed to fill the wiring line groove. Then, the copper containing metal film outside the wiring line groove is removed to form a second wiring line.

Growing community of inventors

Kanagawa, Japan

Hiroyuki Kunishima