Taiyo Yuden Co., Ltd.

Hiroyuki Kozutsumi

Hideaki Yoshida

Mitsunori Katsu

Masayuki Satou

A reconfigurable device and an analog circuit are formed on a single chip so that the analog circuit can be controlled by the reconfigurable device. A reconfigurable semiconductor device () includes a plurality of logic sections () and an analog section (). The plurality of logic sections () are connected to each other by an address line or a data line. The analog section () includes a plurality of input/output sections and an output amplifier. Each of the logic sections () includes a plurality of address lines, a plurality of data lines, a memory cell unit, and an address decoder that decodes an address signal and that outputs a decoded signal to the memory cell unit. The plurality of logic sections () and the analog section () are mounted in the same chip package.

Reconfigurable semiconductor device

A reconfigurable operational amplifier includes: a first signal input terminal; a second signal input terminal; an output terminal; an operational amplifier having a non-inverting input, an inverting input, and an output; a negative feedback circuit path from the output of the operational amplifier to the inverting input of the operational amplifier; a first input circuit path from the first signal input terminal to the non-inverting input of the operational amplifier; a second input circuit path from the second signal input terminal to the inverting input of the operational amplifier; an output circuit path from the output of the operational amplifier to the output terminal; and logic units, wherein one or more of the logic units are provided in at least one of the negative feedback circuit path, the first input circuit path, the second input circuit path, and the output circuit path.

Reconfigurable operational amplifier

A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.

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Tokyo, Japan

Hiroyuki Kozutsumi