Kabushiki Kaisha Toshiba

Hiroyuki Koinuma

Haruki Toda

Toshiki Hisada

Koichi Magome

Kiminobu Suzuki

Atsushi Sueoka

Yutaka Shirai

Shigeo Ohshima

Masahiro Yoshihara

Makoto Takahashi

Toshiyuki Kouchi

Katsumi Abe

Kaoru Nakagawa

Kazuhide Yoneya

Naokazu Miyawaki

Hiroshi Sahara

Katsushi Nagaba

Masakazu Kiryu

Kenji Komatsu

Chikahiro Nakai

The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory, and an interface circuit which controls the first and second memories as one burst transfer memory, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.

Burst transfer memory

A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.

Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit

A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2.sup.n in both sequences. The burst length of the counter circuit may be changeable, and the counter circuit may output a signal indicating whether the count number has reached the burst length.

Counter circuit and semiconductor memory having counter circuit as

A semiconductor integrated circuit includes an input circuit for receiving an input signal from the outside, an internal circuit connected to the input circuit, an output circuit connected to the internal circuit for outputting an output signal to the outside, a power supply line connected to each of the circuits, a power supply terminal connected to the power supply line, a first ground conductor connected to the input circuit, a second ground conductor separated from the first ground conductor and connected to the internal circuit, a first ground terminal connected to the first ground conductor and a second ground terminal connected to the second ground conductor. Because of the provision of the ground conductor exclusively for the input circuit, malfunction of the input circuit due to power supply fluctuations is prevented and an operation margin is increased.

Semiconductor integrated circuit

A semiconductor memory device has one redundant memory cell block selection fuse circuit block for replacing a plurality of normal memory cell blocks with one or more redundant memory cell blocks. The number of the redundant memory cell block selection fuse circuit blocks is thereby reduced enough to restrain an increase in chip area. A lesser number of normal word lines than the number of normal word lines possessed by one normal memory cell block controlled by one normal decoder are set as a minimum replace unit, and a degree of replacing freedom can be improved.

Semiconductor memory device

The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.

Intermediate potential generation circuit

A semiconductor memory includes a plurality of memory cells aligned in rows and columns, a plurality of bit lines respectively connected to the columns of the plurality of memory cells, a plurality of switch circuits each having one end connected to a corresponding one of the plurality of bit lines, the plurality of switch circuits being selectively turned on in accordance with a column address signal input from an outside to identify each of the columns, a data line to which the other end of each of the plurality of switch circuits is commonly connected, a pulse generation circuit for detecting a change in level of the column address signal with respect to first and second circuit thresholds different from each other to generate a pulse signal, the first circuit threshold being used for detecting a change in address signal from one level to the other level, and the second circuit threshold being used for detecting a change in address signal from the other level to one level, and a data detection circuit, connected to the data line and controlled by the pulse signal generated in accordance with the pulse generation circuits, for amplifying a potential of the data line to detect data.

Semiconductor memory

A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is transferred, a transfer gate to connect the first bit line to the first node and the second bit line to the second node, a sense amplifier located between the first node and the second node, an equalizer for equalizing the first node and the second node located between the first node and the second node, a voltage booster for boosting the control signal for the transfer gate and the equalizer. In the DRAM, the control signals for the transmisiion gate and the equalizer are set at V.sub.CC during the precharge cycle, and boosted above V.sub.CC in the activation cycle after the precharge cycle, and the control signal for the transfer gate is changed to V.sub.CC and the control signal for the equalizer is changed to the ground potential V.sub.SS in synchronization with a selection of the word line.

Semiconductor integrated circuit having a voltage booster and

An output buffer generates '1' or '0' data based on control signals VA and VB transferred from memory cells through a DQ gate in a DRAM. The output buffer has first and second discharge circuits, and a first output transistor (PMOS Transistor). The second discharge circuit stops discharging the gate of the first output transistor after the voltage on the gate drops below the threshold voltage of the first output transistor and the first output transistor turns ON. After this time, only the first discharge circuit discharges the gate of the first output transistor. Further, the output buffer has first and second precharge circuits, and a second output transistor (NMOS transistor). The second precharge circuit stops charging the gate of the second output transistor after the voltage on the gate increases above the threshold voltage of the second output transistor and the second output transistor turns ON. After this time, only the second discharge circuit continues charging the gate of the second output transistor.

Output buffer

A semiconductor memory device having a plurality of bits includes an input buffer for receiving external data, a first write circuit for inputting a first control signal, and an output of the input buffer, and outputting the result on a first data line. A second write circuit inputs a second control signal and the result from the first data line, and outputs another output on a second data line. In a data writing operation, the second control signal is used commonly for at least two bits. The first write circuit sets the first data line to a fixed potential state when the first control signal is effective. In response to the fixed potential status on the first data line, the second write circuit sets the second data line to a potential state in which the second control signal is disregarded. A write per bit mode operation is controlled by controlling the second write circuit through a first data line. A control signal for controlling the write circuits can be used commonly for a plurality of bits, so that the number of control signals for controlling the write circuits can be reduced and thereby a pattern area required for wiring can be reduced.

A semiconductor integrated circuit device having a high-efficiency transfer gate and which is applicable to a DRAM which has voltage-raised word lines configured from a data retention node, a data line that is precharged to a required level, a MOS transistor with the source and the drain each connected to a data line and a data retention node, a sense amplifier that amplifies the data that has been transferred to the data line via this MOS transistor a step-up circuit that applies a voltage that is higher than the drain voltage when compared with an absolute value, to the gate of the MOS transistor, and a step-down circuit for reducing the absolute value of a gate voltage of the MOS transistor at the timing of activation of the sense amplifier.

Semiconductor integrated circuit device for high-speed transmission of

A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.

Serial input/output semiconductor memory including an output data latch

A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.

Reference potential generating circuit

In the buffer circuit for an integrated circuit according to this invention a load MOS transistor and a drive MOS transistor are connected in series between a power source potential node and a ground potential node of the integrated circuit. A constant current circuit means connected in series with a circuit including the load MOS transistor and the drive MOS transistor.

Buffer circuit for minimizing noise in an integrated circuit

This invention provides a high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node; a discharge enhancement mode MOS transistor for discharging the potential of the high potential node, having one end connected to the ground potential, the other end connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between the high potential node and the high potential hold transistor; and charge-discharge means for charging and discharging a potential of a gate of the field relaxation transistor.

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Yokohama, Japan

Hiroyuki Koinuma