Spansion Llc.

Advanced Micro Devices Corporation

Sandisk Technologies Inc.

Cypress Semiconductor Corporation

Fujitsu Corporation

Globalfoundries Inc.

Hiroyuki Kinoshita

Yu Nan Sun

Kuo-Tung Chang

Chungho Lee

Angela Tai Hui

Ning Cheng

Unsoon Kim

Chi K Chang

Wei Zheng

Ashot Melik-Martirosian

Kyunghoon Min

Hiroyuki Ogawa

Minghao Shen

Fred Cheung

Fei Wang

Huaqiang Wu

Jayavel Pachamuthu

Tuan Duc Pham

Cyrus E Tabery

Vinod Robert Purayath

Timothy J Thurgate

Jeff P Erhardt

Minh Van Ngo

George Matamis

Mark S Chang

Kashmir S Sahota

Wenge Yang

YongZhong Hu

Amol Ramesh Joshi

Inkuk Kang

Marika Gunji-Yoneoka

Kelwin Ko

Raghuveer S Makala

Masaaki Higashitani

Yanli Zhang

James K Kai

Shenqing Fang

Mark W Randolph

Chih-Yuh Yang

Tazrien Kamal

Jean Yee-Mei Yang

Harpreet Kaur Sachar

Tadashi Nakamura

Hideki Komori

Christopher Foster

Ramkumar Subramanian

Johann Alsmeier

Mark T Ramsbey

Peter Rabkin

Henry Chin

Henry Chien

Yao-Sheng Lee

Takashi Whitney Orimoto

Yi He

Yider Wu

Murshed Chowdhury

Meng Ding

Wenmei Li

Jin Liu

Yuan Zhang

Emmanuil Lingunis

Michael A VanBuskirk

Cinti Xiaohua Chen

Weidong Qian

David Michael Rogers

Michael Brennan

Hsiao-Han Thio

Matthias Baenninger

Kazuya Tokunaga

Jiyin Xu

Mimi Xuefeng Qian

Eli Harari

Sameer S Haddad

Rahul Sharangpani

Calvin T Gabriel

Richard M Fastow

Fei Zhou

Senaka Kanakamedala

Dawn M Hopper

Simon S Chan

Michiaki Sano

Rinji Sugino

Krishnashree Achuthan

Satoshi Shimizu

Jixin Yu

Jaeyong Park

Daxin Mao

Kensuke Yamaguchi

Christy M-c Woo

Christopher H Raeder

Jihwan Choi

King Wai Kelwin Ko

Kazutaka Yoshizawa

Atsushi Suyama

Shigehisa Inoue

Wai Lo

Dai Iwata

Kazuhiro Mizutani

Fred T K Cheung

Kazuto Watanabe

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

Three-dimensional nor array and method of making the same

A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.

Three-dimensional memory device containing etch stop structures and methods of making the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers.

Three-dimensional memory device containing a vertical semiconductor channel containing a connection strap and method of making the same

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

A three-dimensional memory device includes semiconductor devices located on a semiconductor substrate, lower interconnect level dielectric layers embedding lower interconnect structures, an alternating stack of insulating layers and electrically conductive layers overlying the lower interconnect level dielectric layers and including stepped surfaces, memory stack structures vertically extending through the alternating stack, and contact via structures extending downward from the stepped surfaces through underlying portions of the alternating stack to the lower interconnect structures. Each of the contact via structures laterally contacts an electrically conductive layer located at the stepped surfaces, and provides electrical interconnection to an underlying semiconductor device. A top portion of each contact via structures contacts an electrically conductive layer, and is electrically isolated from other underlying electrically conductive layers.

Three-dimensional memory device including contact via structures that extend through word lines and method of making the same

Multiple tier structures including a respective alternating stack of insulating layers and electrically conductive layers is formed over a substrate. A memory opening fill structure extends through the alternating stacks, and includes a vertical semiconductor channel and a memory film. A support pillar structure extends through at least an upper alternating stack, and includes a dummy memory film and a dummy memory film. The support pillar structure may be narrower than the memory opening fill structure at a bottommost layer of the upper alternating stack. Additionally or alternatively, the dummy memory film may be located above a horizontal plane including a topmost surface of a lower alternating stack. Optionally, another support pillar structure including a dielectric material may be provided underneath the support pillar structure in the lower alternating stack. A dielectric material can be provided at levels of the lower alternating stack in a support pillar structure to reduce inter-level leakage current.

Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same

Support pillar structures for leakage reduction in a three-dimensional memory device

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers.

Three-dimensional memory device having L-shaped word lines and a support structure and methods of making the same

Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.

Method of selectively depositing floating gate material in a memory device

Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Air gap isolation in non-volatile memory

An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

Dual storage node memory

High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Metal control gate structures and air gap isolation in non-volatile memory

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

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San Jose, CA, United States of America

Hiroyuki Kinoshita