Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Other

Hiroyuki Kida

Mitsuru Watabe

Shigeki Morinaga

Hideo Maejima

Keiichi Kurakazu

Norio Nakagawa

Hisashi Kaziwara

Junichi Tatezaki

Takeshi Asai

Shiro Baba

Satoshi Masuda

Yugo Kashiwagi

Tetsuaki Nakamikawa

Masahisa Narita

Shunpei Kawasaki

Yoshikazu Aoto

Shinji Kawashima

Yoshiaki Naruse

Naoki Yashiki

Masaru Sugai

Nobuo Shibasaki

Mamoru Ohba

Seiji Kamada

Masahiro Tsuchiya

Toshiyuki Tojo

Takeshi Ohkubo

Hiroyuki Matsuura

Masanobu Kawamura

Ikuro Masuda

Takashi Maruyama

Shirou Baba

Tooru Komagawa

Susumu Kaneko

Koichi Tomobe

Yuji Matsushita

Hideto Suzuki

A memory is configured such that two operational modes, including a high-speed access mode in which current dissipation amount is large, but a high-speed access is possible, and a small current mode in which an access speed is lower than that in said high-speed access mode, but the current dissipation amount is small, are provided in the memory. The memory includes a control circuit for executing one of the two operational modes for the memory, in accordance with a mode designation signal sent from the outside of the memory.

Memory with plurality of blocks each accessed selectively with either one of two operational modes to reduce current dissipation using values of register bits set by an instruction signal

In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching timings of the PMOS transistors or the NMOS transistors, which are connected in series, to differ from each other, thereby improving the noise-resistant performance of a semiconductor integrated circuit.

CMOS circuit

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

Data processor providing fast break in program execution

In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.

Method and apparatus for controlling timing of execution of saving and

System for obtaining strict solution in accordance with accuracy of

A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.

Method of forming a signal wave from first and second waveform data

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Coprocessor executing pipeline control for executing protocols and

A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instruction word read out of the main memory into an intermediate machine word having the orthogonal format, and addresses a microprogram memory in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorporates a plurality of register sets so that each different task can use an individual register set, and a memory for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.

Data processing system with device for arranging instructions

Finely adjustable signal wave forming circuit including complementary

A bus error ascribable to a bus master module other than a central processing unit (CPU) is set as a specified factor for an exception process. When the exception process is requested, the CPU carries a corresponding service program for the exception process into execution without executing a process for altering and setting mask bits as is executed for an interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by the interrupt request etc. accepted before the bus error, and besides, a period of time which is expended before the start of the run of a service program corresponding to the bus error is shortened, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module other than the CPU is enhanced.

Bus error processing system having direct bus master/CPU communication

A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program excution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

Data processor with fast break in program execution by selectively

A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.

Data processing method and apparatus having plural bus interfaces

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Hitachi, Japan

Hiroyuki Kida