Kabushiki Kaisha Toshiba

Hiroyuki Kamijoh

Yoshio Ozawa

Katsuya Okumura

Kikuo Yamabe

Kazuhiko Hashimoto

Kaoru Hama

Ichiro Yoshii

A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

Growing community of inventors

Sagamihara, Japan

Hiroyuki Kamijoh