Sony Corporation

Sony Semiconductor Solutions Corporation

Hiroyuki Iwaki

Kenichi Nakanishi

Yasushi Fujinami

Ken Ishii

Tatsuo Shinbashi

Ryoji Ikegaya

Naohiro Adachi

Yoshiaki Inada

Hideaki Okubo

Yasuaki Hisamatsu

Hirotaka Murakami

Tetsuya Yamamoto

Yusuke Oike

Ken Koseki

Mamoru Sato

Tsunenori Shiimoto

Haruhiko Terada

Takayuki Toyama

Hiroyuki Taguchi

Hiroyuki Terakago

Kentarou Mori

Matatoshi Honjo

Akiko Fujiwara

Kenichi Matsunaga

Yukio Fujita

A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.

Memory controller, memory, memory system, information processing system, and method of control thereof

The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

Memory controller, storage device, information processing system, and memory control method

The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

Memory controller, memory system, and information processing system

A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

Encoding device, memory controller, communication system, and encoding method

Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Storage control apparatus, storage apparatus, and storage control method

A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.

Storage device, storage system, and method of controlling storage device

There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.

Storage apparatus, memory controller, control method for storage apparatus, and program

A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.

Column A/D converter, column A/D conversion method, solid-state imaging element and camera system

A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer.

Storage control device, storage device, information processing system, and storage control method

A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device comprises a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

A/D converter, A/D conversion method, solid-state imaging element and camera system

The present invention is to provide an A/D conversion device, a solid-state image-capturing device, and an electronic device capable of removing fixed pattern noise, capable of preventing an image from being corrupted, capable of generating an appropriate carry signal during bit shift, and capable of avoiding bit inconsistency even when the frequency of the carry signal increases due to the bit shift. A reading unit includes a comparator configured to compare the analog signal potential with a reference signal of which slope is variable, a counter latch unit capable of AD conversion based on processing according to the output of the comparator, and a bit shift function unit capable of bit-shifting the digital data obtained by the counter latch unit, and when digital Correlated Double Sampling (CDS) is performed with a first signal and a second signal having different bit precisions obtained from the comparison with reference signals of different slopes, the bit shift function unit bit-shifts the first signal or the second signal.

A/D conversion device, solid-state image-capturing device, and electronic device

A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

A solid-state imaging device includes: a pixel section formed by pixels performing photoelectric conversion arranged in a matrix; a pixel signal readout section capable of column-parallel processing including an A/D conversion function for reading out a pixel signal from the pixel section and performing analog-digital conversion of the signal, the pixels being read in groups; a voltage sampling section sampling a bias voltage generated by an internal or external voltage generating circuit for a period in accordance with a control signal and supplying the sampled bias voltage to the pixel signal readout section; and a control section controlling the signal readout operation of the pixel signal readout section and the voltage sampling operation of the voltage sampling section. The pixel signal readout section includes a functional portion. The control section exercises control such that the voltage sampling operation is performed in a period other than at least either of a period in which an analog signal is read out or in which A/D conversion is carried out.

Solid-state imaging device, method of driving the device, and camera system with varied timing of sampling period for sampling a bias voltage during pixel readout

Disclosed herein is a data transfer circuit including, a plurality of data transfer lines, a plurality of data outputting sections, a plurality of data holding sections, a data-acquiring-clock supplying section a clock supplying section, and a column scan section.

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Kanagawa, Japan

Hiroyuki Iwaki