Epson Imaging Devices Corporation

Sony Corporation

Sanyo Electric Co., Ltd.

Japan Display Inc.

Japan Display West Inc.

Sanyo Epson Imaging Devices Corp.

Hiroyuki Horibata

Michiru Senda

Reduction in efficiency of a power supply circuit in a display device is prevented. A positive power supply generation circuit and a negative power supply generation circuit are placed close to a terminal portion to which a drive clock and a power supply electric potential are applied externally. The terminal portionis formed in an edge portion of the TFT glass substrate. That is, the positive power supply generation circuitand the negative power supply generation circuitare placed closer to the terminal portionthan primary circuits of the liquid crystal display device, which are the pixel portion, the horizontal drive circuitand the vertical drive circuit. With this, there is obtained a layout that minimizes wiring loads (resistive and capacitive loads associated with wirings to provide the power supply and the drive clock) to prevent reduction in circuit efficiency.

Display device with electronic equipment therewith

Display device and electronic equipment therewith

A size of a power supply circuit in a liquid crystal display device is reduced while an efficiency of the circuit is improved. The power supply circuit is formed on a TFT substrate of a liquid crystal panel and its output is provided to a vertical drive circuit. The power supply circuit is composed of a DC-DC converter that generates a positive power supply electric potential and a DC-DC converter that generates a negative power supply electric potential. The DC-DC converters are driven by a common electrode signal VCOM. The DC-DC converter that generates the positive power supply electric potential outputs VCOMH&#xd7;2, and the DC-DC converter that generates the negative power supply electric potential outputs VCOMH&#xd7;(&#x2212;1). Thus electric potentials which are suitable to turn pixel transistors on and off are made available.

Liquid crystal display device and power supply circuit

An amplifier circuit and display device utilizing the amplifier circuit are provided. The amplifier circuit comprises a buffer amplifier which stabilizes an input signal and outputs a stabilized output signal. By supplying to the input terminal of the buffer amplifier, a voltage derived by adding a difference between the input signal and the output signal to the input signal, it is possible to change the input signal level in accordance with the deviation of the buffer amplifier, which allows correction of the output level to a suitable level.

Amplifier circuit and display device

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.

Display

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.

In a display device with a buffer amplifier which receives an input signal on a positive input terminal, has an output terminal connected to a negative input terminal, and outputs a stabilized output signal, a switch for connecting the positive input terminal and the output terminal is provided. By switching the switch ON, the output of the buffer amplifier is set close to the input.

Display device

An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents Iand Iwhen a clock DCCLK is inverted, resistances Rof a wiring, Rof a wiringand Rof a wiringare set so as to satisfy relations R&#x3e;Rand R&#x3e;R. That is, the through currents Iand Ican be suppressed by reducing the resistances Rand Rso that electric potentials Vand Vare quickly inverted when the clock DCCLK is inverted. Also, the through current Ican be suppressed to suppress the reduction in the positive output electric potential VPP by setting the resistance Rto be larger than either of the resistances Rand R

Power supply circuit and display device therewith

A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.

A level shift circuit basically has a configuration connecting two CMOS inverter circuits in parallel, furnishes an input signal to a control terminal of the inverter circuit, obtains an output signal from an output terminal of the inverter circuit, and has a function for level shifting the voltage amplitude of the input signal to the voltage amplitude of the supply voltage of the inverter circuit. The signal that is input by the gate terminal of an n-channel transistor arranged in each of two current paths forming the level shift circuit is not a direct input signal but a signal that is supplied by adding an offset corresponding to the threshold of each n-channel transistor with respect to the voltage amplitude of the input signal via the input voltage converter circuit.

Level shift circuit

A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C, C, Cand Cis connected to a common node. The capacitors C, C, Cand Chave capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST, ST, ST, ST, STand ST, and selects and outputs either a first reference electric potential Vor a second electric potential Vaccording to a value of each bit of the digital signals D, Dand D. Each of transfer transistors TT, TTand TTtransfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C, Cand C, respectively, in response to a start pulse STP. Each of reset transistors RT, RT, RTand RTconnects the terminal with the other terminal of corresponding each of the capacitors C, C, Cand C, and applies the first reference electric potential Vto both the terminal and the other terminal in response to a reset pulse RST.

D/A converter and liquid crystal display device

Data of a zerobit is supplied via a charge control transistor for the zerobit to a corresponding capacitor, data of a first bit is supplied via a charge control transistor for the first bit to a corresponding capacitor, and data of a second bit is supplied via a charge control transistor for the second bit to a corresponding capacitor. The capacitors for the zerobit, first bit, and second bit have capacitances which are set in a ratio of 1:2:4 and capabilities of the corresponding charge control transistors for respective bits are set in a ratio of 1:2:4. With this structure, charging of capacitors corresponding to the bits can be performed under similar conditions.

Growing community of inventors

Gifu, Japan

Hiroyuki Horibata