Fujitsu Corporation

Ea Pharma Co., Ltd.

Ajinomoto Co., Ltd.

Hiroyuki Higuchi

Kenichi Ogawa

Hidetoshi Matsuoka

Hirokazu Hagio

Satoshi Aburatani

Hiroaki Kameyama

Hiroaki Iwashita

Shinichi Sazawa

Yutaka Tamiya

Yuzi Kanazawa

Akira Yabuki

Yu Liu

Yoshinori Tomita

Shun Kohata

A non-transitory computer-readable recording medium storing a display control program for causing a computer to execute processing, the processing including: determining priorities of a plurality of facilities positioned within a specific area according to a value related to congestion determined on the basis of the upper limit number of people in each of the plurality of facilities and the number of visitors calculated on the basis of an image captured in each of the plurality of facilities; selecting a specific number of facilities from the plurality of facilities on the basis of the determined priorities; and displaying, for each of the specific number of selected facilities, a position on a map and alert information according to the value related to the congestion.

Computer-readable recording medium storing display control program, display control method, and display control apparatus

The disclosed pharmaceutical preparation comprises a compound represented by the chemical formula (A) or a pharmaceutically acceptable salt thereof, which is dispersed in a matrix consisting of a water-soluble high molecular weight substance; and Crospovidone: The pharmaceutical preparation is excellent in the solubility and the storage stability even if the amount of the compound or the salt included in each individual dosage unit is increased.

Pharmaceutical preparation comprising phenylalanine derivative

The disclosed pharmaceutical preparation comprises a compound represented by the chemical formula (A) or a pharmaceutically acceptable salt thereof, which is dispersed in a matrix consisting of a water-soluble high molecular weight substance; and Crospovidone:  The pharmaceutical preparation is excellent in the solubility and the storage stability even if the amount of the compound or the salt included in each individual dosage unit is increased.

In an encoding method, data segments and encoding information which indicates encoding patterns each representing a set of data segments used for a predetermined encoding calculation are acquired. An encoded data piece is generated by performing the predetermined encoding calculation based on each encoding pattern, and is stored in the memory. A first encoding pattern for generating the encoded data piece is compared to a second encoding pattern for a next encoding calculation, and the next encoding calculation is performed by using the encoded data piece corresponding to the first encoding pattern when at least a part of the second pattern is common with the first encoding pattern.

Encoding apparatus and encoding method

A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

Semiconductor memory of which defective cell is replaceable with redundant cell and manufacturing method of semiconductor memory

A disclosed method includes: converting, for each sample point, a set of performance item values for a sample point into coordinate values of a mesh element containing the set among plural mesh elements obtained by dividing a space mapped by the performance items; generating a binary decision graph representing a group of the coordinate values of the sample points; calculating the number of sample points including second sample points that dominates a first sample point and the first sample point, by counting the number of paths in the binary decision graph from a root node to a leaf node representing '1' through at least one of certain nodes corresponding to coordinate values that are equal to or less than coordinate values of the first sample point; and calculating a yield of the first sample point by dividing the calculated number by the number of the plural sample points.

Method and apparatus for calculating yield

A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.

Waveform analyzer and waveform analysis method

A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaining and the calculating plural times while changing the reference candidate value set.

Simulation parameter correction technique

The present invention provides solid dispersions or solid dispersion pharmaceutical preparations containing a water-soluble polymeric substance(s) and a phenylalanine compound of the formula (1) or pharmaceutically acceptable salts thereof, wherein A represents the formula (2) and the like, B represent an alkoxy group and the like, E represents a hydrogen atom and the like, D represents a substituted phenyl group and the like, T, U and V represent a carbonyl group and the like, Arm represents a benzene ring and the like, R1 represents an alkyl group and the like, R2, R3, and R4 may be the same or different from one another and each represent a hydrogen atom, a substituted amino group and the like, and J and J' represent a hydrogen atom and the like; production methods thereof; and solubilized pharmaceutical preparations containing a solubilizer(s) and the compound (I) or pharmaceutically acceptable salts thereof. According to the solid dispersion pharmaceutical preparations or solubilized pharmaceutical preparations, though they contain the phenylalanine compound of the formula (1) that is a poorly-soluble drug as an active ingredient, the pharmaceutical preparations having high solubility and oral absorbability can be obtained. 

Solid dispersions or solid dispersion pharmaceutical preparations of phenylalanine derivatives

A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Computer readable non-transitory medium storing design aiding program, design aiding apparatus, and design aiding method for determining performance index of an integrated circuit in worst case operation conditions

Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values from sequential circuit elements in the target circuit are substituted into each of the clock gate functions to obtained clock gate function values. Combinations of the clock gate function values form individual clock gating states. Each clock gating state indicates an activation state of each of the local clocks, collectively. A table indicating correlations between the combinations of output values and the clock gating states is generated and from the conversion table, a group that includes all of the clock gating states possible is output.

Clock gating analyzing apparatus, clock gating analyzing method, and computer product

In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an input pattern causing the extracted pair to perform concurrent transition. When an input pattern causing concurrent transition is found, the searching unit determines the extracted pair to be a pair capable of concurrent transition (concurrent transition pair), and holds the input pattern causing concurrent transition. When an input pattern causing concurrent transition is not found, the searching unit determines the extracted pair to be a non-concurrent transition pair. An input pattern operation ratio calculating unit calculates an input pattern operation ratio for each input pattern causing concurrent transition. A detecting unit detects an input pattern yielding the highest input pattern operation ratio. An output unit puts out the detected input pattern, non-concurrent transition pairs, etc.

LSI analysis method, LSI analysis apparatus, and computer product

An apparatus for creating a simplified false-path description on a false path among paths in a target circuit extracts, from descriptions on the paths, a target path description on a target path. The apparatus judges whether the target path is a false path based on the target path description. The apparatus identifies, when it is judged that the target path is a false path, a sufficient set of elements from elements included in the target path. The settings for causing every element in the sufficient set to transmit a signal conflict. The apparatus creates the simplified false-path description on the false path by deleting, from the target path description, a description on elements that are not included in the sufficient set.

Method and apparatus for creating simplified false-path description on false path, and computer product

A false path detection program whereby passing points of signal lines constituting false paths are directly detected, thereby shortening the processing time necessary for the false path detection and the processing time of tools utilizing false path information. A storing section stores, in a storage device, circuit information about a circuit designed by a designer. A signal value generating section generates an impossible signal value with respect to a signal line in the circuit. A signal propagation inspecting section assigns the signal value generated by the signal value generating section to an input of a gate connected to the signal line with respect to which the signal value has been generated, and examines whether signal is propagated through the other input of the gate only when accompanied by the signal value. If signal is propagated through the other input of the gate, a passing point acquiring section acquires a passing point of the other signal line connected to the other input of the gate. A false path specifying section specifies a false path by the passing point acquired by the passing point acquiring section.

False path detection program

A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

Growing community of inventors

Kawasaki, Japan

Hiroyuki Higuchi