Japan Display Inc.

Panasonic Liquid Crystal Display Co., Ltd.

Panasonic Intellectual Property Corporation of America

Hitachi Displays, Ltd.

Hiroyuki Higashijima

Takahiro Ochiai

Mitsuru Goto

Hiroko Sehata

Shuuichirou Matsumoto

Yoshihiro Kotani

Motoharu Miyamoto

A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.

Shift register circuit

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Bidirectional shift register circuit

A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.

Bidirectional shift register and image display device using the same

A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point Nis at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time tto t) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point Nof (n+4)-th unit register circuit to H level at the time of start of the backward shift.

A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point Nis at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time tto t) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point Nof (n+4)-th unit register circuit to H level at the time of start of the backward shift.

A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors TA, TB are connected between the output terminal OUT and AC power sources VA, VB. At least one of TA, TB is brought into ON state and TA, TB are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where TA, TB are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where TA, TB are in OFF state.

Drive circuit for display panel, and display device

A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.

Display device

A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.

A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A &#x3bb;th stage of unit register circuit () has two set terminals connected to respective outputs of (&#x3bb;&#x2212;1)th and (&#x3bb;+1)th stages and two reset terminals connected to respective outputs of (&#x3bb;+2)th and (&#x3bb;&#x2212;2)th stages. The unit register circuit () sets, when a pulse is input to any one of the set terminals, a reference point Nto an H level, and, when a pulse is input to any one of the reset terminals, Nto an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

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Konosu, Japan

Hiroyuki Higashijima