Kabushiki Kaisha Toshiba

Canon Kabushiki Kaisha

Agc Inc.

Kioxia Corporation

Asahi Glass Company, Limited

Toshiba Memory Corporation

E.i. Dupont De Nemours and Company

Hiroyuki Hara

Yasuhiro Sugimoto

Shinichi Nakamura

Shinichiro Shiratake

Tetsuya Fujita

Takayasu Sakurai

Mototsugu Hamada

Shuichiro Sugimoto

Fumitoshi Hatori

Yukihito Oowaki

Atsushi Kawasumi

Chen Kong Teh

Haruo Machida

Masashi Kuroshima

Tamio Ikehashi

Hiroaki Inoue

Motohiro Takemura

Katsuhiro Seta

Takao Hirono

Yoshinori Watanabe

Kojiro Katayama

Makoto Kawashima

Junichi Hirose

Masataka Matsui

Takashige Maekawa

Reika Fukuda

Takayuki Miyazaki

Yasunori Tanaka

Hiroyuki Takenaka

Masaji Ueno

Toshikazu Sei

Akira Isobe

Sho Masuda

Yukio Kamatani

Azuma Suzuki

Kazunori Sugiyama

Kazushi Ohmori

Yukiko Shiota

Yuzuka Kamijo

Chenkong Teh

Yuuichi Oomori

Shoichi Shimizu

Tetsu Nagamatsu

Akihiko Chiba

Ryoichiro Sato

Michinori Nakamura

Junsuke Kawana

Eiji Morimoto

Takeshi Sugoh

Yoshinori Suzuki

Barry E Taylor

Motosugu Hamada

Hideki Tomizawa

Kazushi Omori

Yukiko Yoshimoto

Kazuki Okawa

Marc H La Branche

Mika Sugimoto

Yoshinori Nitta

Yuzuka Yoshioka

A liquid repellent composition which can provide an article with good alcohol repellency is provided. A liquid repellent composition comprising a fluorinated polymer and an aqueous medium, wherein the fluorinated polymer comprises units based on a monomer a, units based on a monomer b and units based on a monomer c. Monomer a: a compound represented by CH═CH—R(wherein Ris a Cperfluoroalkyl group). Monomer b: a fluorine-free nonionic surfactant having a polymerizable carbon-carbon double bond. Monomer c: another monomer copolymerizable with the monomer a and the monomer b.

Liquid repellent composition, method for producing same, and article

A water- and oil-proofing composition which can provide an article with high utility oil resistance is provided. A water- and oil-proofing composition comprising a fluorinated polymer comprising units based on the following monomer (a) and units based on the following monomer (b), a fatty acid ester of polyglycerin and an aqueous medium: Monomer (a): a compound represented by CH═CH—R(wherein Ris a Cperfluoroalkyl group). Monomer (b): a monomer copolymerizable with the monomer (a).

Water- and oil-proofing composition, method for its production, article and water- and oil-proof paper

To provide a polymer which can provide a water- and oil-proof paper with excellent water and oil resistance. A polymer comprising the following units a, and at least the following units b among the following units b and the following units c, wherein the ratio of units a to all the units in the polymer is from 28 to 70 mol %, the total ratio of units b and units c to all the units in the polymer is from 30 to 72 mol %, and the ratio of units b to the sum of units b and units c is at least 45 mol %:

Polymer, method for producing same, water- and oil-proofing composition, article, and water- and oil-proof paper

A method for producing a water/oil repellent composition can produce an article which is excellent in the oil repellency while maintaining the water repellency and the heavy-rain durability. The method includes mixing an emulsion of a polymer having from 10 to 50 mass % of units based on a monomer having a perfluoroalkyl group per all units and an emulsion of a monomer component containing at least 80 mass % of a monomer having a perfluoroalkyl group so that the proportion of the mass of the polymer will be from 50 to 99 mass % per the sum of the mass of the polymer and the total mass of the monomer component and then polymerizing the monomer component. The monomer component includes emulsified particles in the emulsion of the monomer component. The emulsified particles have an average particle size of from 50 to 600 nm.

Method for producing water/oil repellent composition and method for producing water/oil repellent article

To provide a water/oil repellent article which presents little burden on the environment, while being excellent in water/oil repellency, washing durability of the water repellency and friction durability of the water repellency; a method for producing such a water/oil repellent article; and a water/oil repellent composition and a water/oil repellent kit to be used for producing such a water/oil repellent article. A water/oil repellent article that comprises a substrate and, as adhered to the surface of the substrate, a fluorinated polymer having structural units based on monomer (a) having a Cperfluoroalkyl group, and a specific fluorinated ether compound; a method for producing the water/oil repellent article, which comprises letting the fluorinated polymer and fluorinated ether compound be adhered to the substrate; a water/oil repellent composition which comprises the fluorinated polymer and fluorinated ether compound; and a water/oil repellent kit which comprises a first container accommodating a first liquid containing the fluorinated polymer and a second container accommodating a second liquid containing the fluorinated ether compound.

Water/oil repellent article, method for its production and water/oil repellent composition

Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the third direction; a plurality of second region wirings provided between the second region memory cells; and a control circuit capable of executing a reading operation.

Semiconductor storage device

To provide a fluorinated copolymer dispersion, whereby it is possible to obtain an article being excellent in water-and-oil repellency and less susceptible to a decrease in the water-and-oil repellency by alkali, etc. and which presents little impact to the environment by an organic solvent; a method for its production; and an article which is excellent in water-and-oil repellency and is less susceptible to a decrease in the water-and-oil repellency by alkali, etc. The fluorinated copolymer dispersion comprises an aqueous medium and a fluorinated copolymer dispersed in the aqueous medium, wherein the fluorinated copolymer has units based on the following monomer (a) and units based on the following monomer (b), the proportion of the units based on the monomer (a) being from 20 to 60 mol % to all units constituting the fluorinated copolymer, and the fluorinated copolymer has a number average molecular weight of from 10,000 to 100,000: Monomer (a): a compound represented by CH&#x2550;CH&#x2014;R(Ris a Cperfluoroalkyl group); and Monomer (b): a monomer copolymerizable with the monomer (a).

Fluorinated copolymer dispersion, method for its production and article

A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines.

A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: a substrate having a substrate plane extending in a first direction and a second direction intersecting with the first direction; a first wiring provided above the substrate, the first wiring being provided so that a longitudinal direction extends along the first direction; a second wiring provided above the substrate, the second wiring being separated from the first wiring in the first direction, the second wiring being passed by the same virtual line together with the first wiring, the second wiring being provided so that a longitudinal direction extends along the first direction; a third wiring provided between the first wiring and the second wiring, the third wiring being separated from the first wiring and the second wiring, the third wiring being passed by the same virtual line together with the first wiring and the second wiring, the third wiring being provided so that a longitudinal direction extends along the first direction; a fourth wiring provided above the first wiring, the fourth wiring overlapping with the first wiring when viewed from the above, the fourth wiring being provided so that a longitudinal direction extends along the first direction; a fifth wiring provided over the second wiring and the third wiring, the fifth wiring being separated from the fourth wiring in the first direction, the fifth wiring overlapping with the second wiring and the third wiring when viewed from the above, the fifth wiring being passed by the same virtual line together with the fourth wiring, the fifth wiring being provided so that a longitudinal direction extends along the first direction; a sixth wiring provided over the fourth wiring and the fifth wiring, the sixth wiring overlapping with the fourth wiring and the fifth wiring when viewed from the above, the sixth wiring being provided so that a longitudinal direction extends along the first direction; a plurality of seventh wirings provided between the first wiring and the fourth wiring, between the third wiring and the fifth wiring, and between the second wiring and the fifth wiring, the seventh wirings being provided so that a longitudinal direction extends along the second direction; a plurality of eighth wirings provided between the fourth wiring and the sixth wiring and between the fifth wiring and the sixth wiring, the eighth wirings being provided so that a longitudinal direction extends along the second direction; a plurality of first memory cells provided between the first wiring, the second wiring, and the third wiring and the seventh wirings; a plurality of second memory cells provided between the fourth wiring and the seventh wirings and between the fifth wiring and the seventh wirings, the second memory cells overlapping with the first memory cells when viewed from the above; a plurality of third memory cells provided between the fourth wiring and the eighth wirings and between the fifth wiring and the eighth wirings, the third memory cells overlapping with the second memory cells when viewed from the above; a plurality of fourth memory cells provided between the sixth wiring and the eighth wirings, the fourth memory cells overlapping with the third memory cells when viewed from the above; a first connection wiring provided above the substrate, the first connection wiring being provided at least partially under a portion where the first wiring and the third wiring are separated; a second connection wiring provided between the first wiring and the third wiring so that a longitudinal direction extends along a third direction intersecting with the first direction and the second direction, the second connection wiring connecting the sixth wiring and the first connection wiring; a third connection wiring configured to connect the first wiring and the first connection wiring; a fourth connection wiring configured to connect the third wiring and the first connection wiring; a fifth connection wiring provided above the substrate, the fifth connection wiring being provided at least partially under a portion where the second wiring and the third wiring are separated; and a sixth connection wiring provided between the second wiring and the third wiring so that a longitudinal direction extends along the third direction, the sixth connection wiring connecting the fifth wiring and the fifth connection wiring.

A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.

Semiconductor storage device having alternately stacked bit lines and word lines, and first and second connection wirings to bit line contacts, that extend in opposite directions with respect thereto

To provide a liquid repellent composition whereby a treated article excellent in liquid repellency is obtainable, which is excellent in stability and does not have such a problem as an odor attributable to ammonia or an organic amine; a method for its production; and a method for producing oil resistant paper. The liquid repellent composition comprises a copolymer (A) having structural units derived from a monomer (a) represented by the formula R-Q-X&#x2014;C(O)C(R)&#x2550;CH(Ris a Cperfluoroalkyl group, Q is a divalent hydrocarbon group that does not contain a fluorine atom; X is &#x2014;O&#x2014; or NH&#x2014;, and R is a hydrogen atom, a methyl group or a chlorine atom) and structural units derived from a monomer (b) having an anionic group, alkali metal ions and an aqueous medium; wherein the mass average molecular weight of the copolymer (A) is at most 84,000; at least some of counterions to the anionic groups are alkali metal ions; and the molar ratio of alkali metal ions to anionic groups in the liquid repellent composition is from 0.6 to 1.29.

Liquid repellent composition, method for its production, and method for producing oil resistant paper

A semiconductor memory device includes first wirings above a substrate and extending in a first direction, second wirings above the first wirings and extending in a second direction crossing the first direction, third wirings above the second wirings and extending in the first direction, memory cells between the first and second wirings and between the second and third wirings, a first multiplexer that extends in the second direction, is connected to the first wirings, and is provided in a first region which overlaps with the first, second, and third wirings in a third direction that crosses the first and second directions, and a second multiplexer that extends in the first direction, is connected to the second wirings, and is provided in a second region which overlaps with the first, second, and third wirings in the third direction.

To provide a water/oil repellent composition whereby it is possible to obtain an article which is excellent in each of water-repellency, oil-repellency, washing durability, heavy rain durability and texture, a method for producing said composition, and an article which is excellent in each of water-repellency, oil-repellency, washing durability, heavy rain durability and texture. The water/oil repellent composition comprises a copolymer having units based on a monomer (a), units based on a monomer (b) and units based on a monomer (c), and a liquid medium. Monomer (a): a compound represented by (Z&#x2014;Y)X (Z: a Cperfluoroalkyl group, etc.; Y: a divalent organic group, etc.; n: 1 or 2; X: a polymerizable unsaturated group). Monomer (b): a (meth)acrylate having no polyfluoroalkyl group and having an alkyl group with at least 20 carbon atoms. Monomer (c): a compound represented by CH&#x2550;CRC(O)O&#x2014;[(CHO)(CHO)]&#x2014;H (R: a hydrogen atom or a methyl group, and a/b=1 to 3).

Water/oil repellent composition, method for its production, and article

A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.

Semiconductor integrated circuit

Growing community of inventors

Kanagawa, Japan

Hiroyuki Hara