Elpida Memory, Inc.

Kawasaki Jukogyo Kabushiki Kaisha

Toray Industries, Inc.

National Cancer Center

Ps4 Luxco S.a.r.l.

International Superconductivity Technology Center

Nippon Steel Corporation

Railway Technical Research Institute

Kawasaki Steel Corporation

Tosoh Corporation

Shikoku Electric Power Co., Inc.

Hokuriku Electric Power Company

Hiroyuki Fujimoto

Haruo Kitai

Satoko Kozono

Hiroko Sudo

Takahiro Ochiya

Makiko Yoshimoto

Juntaro Matsuzaki

Masato Murakami

Izumi Takagi

Yasuhiko Ueda

Naoki Koshizuka

Atsuko Miyano

Takeshi Miyazaki

Fumihiko Urabe

Yoshihiro Takaishi

Junpei Kawauchi

Shinpei Iijima

Naomichi Sakai

Hiroshi Takaichi

Akihiro Kondoh

Wataru Usuba

Shoji Tanaka

Yuki Koga

Yuichi Kawamoto

Taisuke Morita

Fumiki Aiso

Hiromasa Fukuyama

Yuki Togashi

Toru Minami

Ken Nagashima

Sang-Im Yoo

Yu Shiohara

Shoichi Kagiya

Terutsugu Oyama

Naomichi Nakamura

Masao Mikasa

Satoru Aihara

This invention provides a kit or device for detection of prostate cancer and a method for detecting prostate cancer. This invention provides a kit or device for detection of prostate cancer comprising a nucleic acid capable of specifically binding to an miRNA in a sample from a subject or a complementary strand thereof and a method for detecting prostate cancer comprising measuring the miRNA in vitro.

Kit, device and method for detecting prostate cancer

An embodiment according to the present invention provides a kit or device for detection of bladder cancer, and a method for detecting bladder cancer. An embodiment according to the present invention relates to: a kit or device for detection of bladder cancer, including a nucleic acid(s) capable of specifically binding to an miRNA(s) or a complementary strand(s) thereof in a sample from a subject; and a method for detecting bladder cancer, including measuring the miRNA(s) in vitro.

Kit, device, and method for detecting bladder cancer

The invention includes: multiple bit lines bto barranged in parallel to each other at a first line pitch; multiple word lines wto warranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines bto b; and multiple capacitors. Respective center positionsof the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.

Semiconductor device having efficient capacitor arrangement

A method for producing a semiconductor device includes: a process for forming a first conductor on a first interlayer insulating film provided on a semiconductor substrate, a process for forming in order a first stopper interlayer film, a second interlayer insulating film, a second stopper interlayer film, and a third interlayer insulating film on the first interlayer insulating film to cover the first conductor, a process for penetrating the third interlayer insulating film, the second stopper interlayer film, and the second interlayer insulating film, and forming a first contact hole having a first inner diameter on a position corresponding to the first conductor, a process for expanding the inner diameter of the first contact hole on the second interlayer insulating film to a second inner diameter larger than the first inner diameter, and a process for forming on the first stopper interlayer film a second contact hole.

Semiconductor device and method for producing same

A memory cell region comprises a first interlayer insulating film having a bit contact hole, a contact plug formed of a first conductor film embedded in the bit contact hole, and a second conductor film which is stacked on the first interlayer insulating film to constitute a bit line connected to the contact plug. A peripheral transistor region comprises a peripheral transistor having a gate insulating film and a gate electrode stack formed on the gate insulating film. The gate electrode stack is provided with a metal gate film formed on the gate insulating film, an upper gate film stacked on the metal gate film, and a third conductor film stacked on the upper gate film. A height from a semiconductor substrate to a top face of the upper gate film is equal to or lower than a height of a top face of the first interlayer insulating film.

Semiconductor device having a memory cell region and a peripheral transistor region

A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor having a second lower diffusion layer, a second upper diffusion layer, and a second gate electrode; a gate wiring connected to the first and second gate electrodes; a first wiring connected to the first lower diffusion layer and second upper diffusion layer; and a second wiring connected to the first upper diffusion layer and second lower diffusion layer.

Semiconductor device having vertical type transistor

A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.

Semiconductor device and method of manufacturing the same

A switching device of a driving power transmission system equipped in an off-road vehicle, including a switching lever configured to switch driving power transmission of the driving power transmission system, and a negative-pressure actuator module that is coupled to the switching lever and is configured to operate the switching lever.

Switching device of a driving power transmission system and an off-road vehicle

In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a third insulation film and the lower pillar is covered with a first insulation film, which is a gate insulation film, from a side surface thereof to the second insulation film. A gate electrode is insulated from an upper conductive layer by the second and third insulation films.

Semiconductor device

A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A gate insulating film is formed on an inside wall of the groove. A buried gate electrode is formed on the gate insulating film and on a bottom portion of the groove. A cap insulating film covering the buried gate electrode is formed in an upper portion of the groove. The cap insulating film has a top surface which is different in level from a top surface of the semiconductor substrate. A first inter-layer insulating film is formed on the top surface of the semiconductor substrate and on the top surface of the cap insulating film. The first inter-layer insulating film with a flat top surface fills a gap in level between the top surface of the semiconductor substrate and the top surface of the cap insulating film.

Method of forming a semiconductor device

A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar.

Semiconductor device and method of forming the same

A semiconductor device includes a first semiconductor pillar, a first insulating film covering a side face of the first semiconductor pillar, a first electrode covering the first insulating film, a second semiconductor pillar, a second insulating film covering a side face of the second semiconductor pillar, and a second electrode covering the second insulating film. The top level of the second electrode is higher than the top level of the first electrode.

Semiconductor device and method of forming semiconductor device

Growing community of inventors

Tokyo, Japan

Hiroyuki Fujimoto