Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Tower Semiconductor Ltd.

Tower Partners Semiconductor Co., Ltd.

Hiroyuki Doi

Yasushi Okuda

Keita Takahashi

Nobuyuki Tamura

Ryohei Miyagawa

Masafumi Doi

Hirotsugu Honda

Takuo Akashi

Katsujirou Arai

Naritsugu Yoshii

Hiroki Takahashi

Takao Yamaguchi

Yutaka Hirose

Mitsuyoshi Mori

Hirohisa Ohtsuki

Motonari Katsuno

Masafumi Tsutsui

Yusuke Sakata

Mitsuo Yasuhira

Yoshiyuki Ohmori

Ken Mimuro

Masahiro Oda

Hitoshi Kuriyama

Hirohisa Otsuki

Takashi Miyake

Yasushi Hazama

A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.

Solid-state imaging device

A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.

Solid-state image pickup device

A solid-state imaging device includes: an epilayer; pixel electrodes; a photoelectric converting film formed above the pixel electrodes and converting incident light into electric signals; a transparent electrode formed on the photoelectric converting film; charge accumulating regions of an n-type each (i) formed in the epilayer to correspond to one of the pixel electrodes, (ii) electrically connected to the one corresponding pixel electrode, and (iii) accumulating signal charges generated by the photoelectric converting film through the photo-electrically conversion; charge barrier regions of a p-type each formed in the epilayer to contact a bottom of a corresponding one of the charge accumulating regions; and charge draining regions of an n-type each formed in the epilayer to contact a bottom of a corresponding one of the charge barrier regions.

Solid-state imaging device and driving method of solid-state imaging device

A solid-state imaging element includes a photodiode formed in an upper portion of a semiconductor substrate to perform a photoelectric conversion, a silicon dioxide film formed on the substrate to cover the photodiode, and a silicon nitride film formed on the silicon dioxide film. The silicon nitride film has a thinner portion smaller in thickness than at least an end portion of the silicon nitride film entirely or partly over the photodiode.

Solid-state imaging element

A solid state imaging device including a pixel region where a plurality of pixel cells--. . . have been formed. When focusing on a red pixel cell whose color filter has the longer transmission peak wavelength and a blue pixel cell whose color filter has the shorter transmission peak wavelength, the distribution of substrate contacts is denser in a region in the vicinity of a photodiode in the red pixel cell than a region in the vicinity of a photodiode in the blue pixel cell.

Solid state imaging device including a semiconductor substrate on which a plurality of pixel cells have been formed

A semiconductor device with a fuseto be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating filmwith high filling capability and a second insulating filmblocking penetration of moisture or impurities. An openingformed in a specific depth through the insulating films on the fuseis coated by a third insulating filmwith the blocking capability. This prevents the penetration of moisture or impurities, and the corrosion of the fuse

Semiconductor device and manufacturing method thereof

A constant voltage device includes n-type and p-type doped layers. The n-type doped layer is formed by heavily doping with an n-type impurity an upper portion of a p-type silicon semiconductor substrate, in an active region defined by an isolating insulator film. The p-type doped layer is formed by doping the region under the n-type doped layer with a p-type impurity. The n-type and p-type doped layers are provided to form two layers in parallel with the substrate surface of the semiconductor substrate, whereby a pn junction formed between the n-type and p-type doped layers creates a diode structure. Impurity concentration in the p-type doped layer is established so that the impurity concentration of a portion adjacent the isolating insulator film is lower that that of the rest.

Semiconductor devices constitute constant voltage devices used to raise internal voltage

A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.

Method for fabricating nonvolatile-semiconductor memory device

A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate.

Method of manufacturing semiconductor device

A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Semiconductor device and method for driving the same

A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

Nonvolatile semiconductor memory device and method for driving the same

A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.

Method for fabricating semiconductor device using a CVD insulator film

A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

After forming a control gate electrode, an interelectrode insulating film and a floating gate electrode of a nonvolatile memory device in a memory region with allowing a conducting film to remain in a logic region, an insulating film for implant protection is formed on a substrate, and ion implantation is carried out to form a source/drain diffusion layer of the nonvolatile memory device. Then, after removing the insulating film for implant protection, the conducting film is patterned into a gate electrode of a logic device. Thereafter, impurity ion implantation is carried out with the gate electrode used as a mask so as to form an LDD diffusion layer of the logic device. At this point, since the insulating film for implant protection has already been removed from the logic region, a shallow PN junction can be formed, resulting in realizing a logic device suitable to refinement.

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Kyoto, Japan

Hiroyuki Doi