Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Renesas Electronics Corporation

Renesas Technology Corp.

Hiroyuki Chibahara

Masahiro Matsumoto

Atsushi Ishii

Masanobu Iwasaki

Naoki Izumi

Yuichi Sakai

Yoshifumi Takata

Kakutaro Suda

Taiki Donen

Satoshi Ochi

Yasutomo Tanihara

Shin Hasegawa

Shuichi Ueno

Keiichi Higashitani

Yuichi Takai

Haruo Furuta

Ryoji Matsuda

Masakazu Okada

Tatsuya Fukumura

Hiroshi Oshita

Shinya Hirano

Takayuki Itotani

The present disclosure aims to provide an electrical contact to which a low boiling point metal is added, the electrical contact being able secure both mechanical strength and conductivity at the same time. The electrical contact according to the present disclosure includes a base material made of Cu, particles of a high melting point substance dispersed in the base material, the particles being made of at least one of a high melting point metal or a carbide of the high melting point metal, and Te and Ti dispersed in the base material, wherein, the Te of 3.5 to 14.5 mass % is added where the total is 100 mass %, and Ti/Te is 0.12 to 0.38.

Electrical contact and vacuum switch tube comprising electrical contact

Provided is a method of manufacturing a contact material, including the steps of: forming a Ni alloy film having a film thickness of 40 nm or more and 110 nm or less on a surface of WC powder having an average particle diameter of 2 &#x3bc;m or more and 10 &#x3bc;m or less by an electroless Ni plating method; performing heat treatment for degassing at a temperature of 500&#xb0; C. or more and 860&#xb0; C. or less; crushing Ni alloy-coated WC powder after the heat treatment; mixing the crushed Ni alloy-coated WC powder and Cu powder having an average particle diameter of 1 &#x3bc;m or more and 100 &#x3bc;m or less; and compressing the resultant mixture, followed by sintering the mixture at a temperature of more than 1,083&#xb0; C. and less than 1,455&#xb0; C.

Contact material, method of manufacturing same, and vacuum valve

In an electric contact including a base material, high-melting-point substance particles, and an intermetallic compound, the intermetallic compound containing a MnX compound (X represents Te or Se) and a compound of a Mn&#x2014;Cu solid-solution phase and X, is dispersed in the base material. If the Vickers hardness of the high-melting-point substance particles is higher than 0 Hv and lower than 200 Hv, the particle diameter of the high-melting-point substance particles is not smaller than 0.1 &#x3bc;m and not larger than 100 &#x3bc;m. If the Vickers hardness of the high-melting-point substance particles is 200 Hv or higher, the particle diameter is not smaller than 0.1 &#x3bc;m and not larger than 10 &#x3bc;m. The mass of X atoms is not lower than 1.5 mass % and not higher than 15 mass %. The atomic weight ratio Mn/(Mn+X) is not lower than 20 at % and not higher than 80 at %.

Electric contact and vacuum interrupter using same

A contact member according to the present invention includes: a contact layer composed of a plate-shaped porous body containing a high-melting-point metal as a main constituent and infiltrated with an infiltrant containing a low-melting-point metal as a main constituent; a contact-layer supporting part composed of the infiltrant; and a contact-part holding conductor composed of the infiltrant, wherein, the porous body is provided with an opening at the center of the contact layer and a portion from the opening to the contact-part holding conductor is continuously and integrally molded with the infiltrant.

Contact member, method for producing the same, and vacuum interrupter

A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

Semiconductor device and method for manufacturing the same

A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

Method for manufacturing a magnetic memory device and magnetic memory device

There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.

Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof

The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.

Method of manufacturing a semiconductor device having a monitor pattern, and a semiconductor device manufactured thereby

There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.

Growing community of inventors

Tokyo, Japan

Hiroyuki Chibahara