Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Fujitsu Corporation

Hiroyuki Chiba

Naoki Hamanaka

Tatsuo Higuchi

Shigeo Takeuchi

Junji Nakagoshi

Yasuhiro Ogata

Taturu Toba

Masaaki Iwasaki

Satoshi Yoshizawa

Naoki Utsunomiya

Masahiko Yamauchi

Kouji Sonoda

Shinichi Shutoh

Shin'ichi Shutoh

Teruo Tanaka

Yasuto Aramaki

Tatsuru Toba

Tomoo Utsumi

Nobuaki Yoshitake

A data reading unit reads inner offset data from an offset reading in an inner direction toward a center of a storage medium and outer offset data from an offset reading in an outer direction toward a circumference of the storage medium. A data comparing unit compares the inner offset data and the outer offset data read by the data reading unit. A data-output control unit that outputs the read-data when a result of comparison by the data comparing unit indicates that the inner offset data matches the outer offset data.

Storage device, data-assurance control device, and data assurance method

An HDC asserts the read gate of an RDC when a read head is positioned in a sector located before a sector that a hot system instructs to read data when seen from the rotation direction of a storage medium. The data that the read head has read from the sector is used to adapt a circuit that constitutes the RDC. However, the data is not transferred to the host system. Such a process is repeated until the read head reaches a position where data stored in a sector whose data has been instructed to read can be read. In this way, time needed to adapt a circuit that constitutes a read channel can be shortened.

Data read device, read method and circuit controlling read device

In a computer system in which nodes are connected to each other via a network, transmission and reception buffers of sender and receiver processes are prepared as resident areas in a main storage. A node of a receiver side notifies, prior to initiation of a communication, a physical address of a data reception area of the node to a node on a sender side. In the node on the sender side, the reported physical address is added to transmission data to transfer a resultant item. On the receiver side, reception data is written in a location of the main storage at the physical address. In the receiver node, the double buffering is employed to prevent an overwriting operation of another node onto the data reception area. The respective nodes achieve partial synchronization with adjacent nodes in chain, thereby automatically establishing synchronization between all nodes. A node on a receiver side notifies prior to initiation of a communication an identifier of a data reception area to a node on a sender side such that the sender node transmits data with the identifier added thereto. In the receiver node, the identifier added to the received data is compared with an identifier added to a data reception area thereof. If mismatching results, interruption is caused in a processor of the receiver node.

Method for interprocessor communication

In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

Partial broadcast method in parallel computer and a parallel computer

In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.

Switching system for transferring broadcast packet held in broadcast

Method for intraprocessor communication

In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.

Inter-processor communication method for transmitting data and processor

Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.

Parallel processor system having computing clusters and auxiliary

Growing community of inventors

Kawasaki, Japan

Hiroyuki Chiba